From cd3cc4749da67a027c8fa0141eca8e7c874c76c2 Mon Sep 17 00:00:00 2001 From: David Lenfesty Date: Wed, 11 Jul 2018 17:46:44 -0600 Subject: [PATCH] Created VXO7803-1000 3v3 power regulator --- Custom-Parts/power_reg.dcm | 3 +++ Custom-Parts/power_reg.lib | 19 +++++++++++++++++++ .../power_reg.pretty/VXO7803-1000.kicad_mod | 16 ++++++++++++++++ 3 files changed, 38 insertions(+) create mode 100644 Custom-Parts/power_reg.dcm create mode 100644 Custom-Parts/power_reg.lib create mode 100644 Custom-Parts/power_reg.pretty/VXO7803-1000.kicad_mod diff --git a/Custom-Parts/power_reg.dcm b/Custom-Parts/power_reg.dcm new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/Custom-Parts/power_reg.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/Custom-Parts/power_reg.lib b/Custom-Parts/power_reg.lib new file mode 100644 index 0000000..99b6c6a --- /dev/null +++ b/Custom-Parts/power_reg.lib @@ -0,0 +1,19 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# VXO7803-1000 +# +DEF VXO7803-1000 U 0 40 Y Y 1 F N +F0 "U" 300 -200 39 H V C CNN +F1 "VXO7803-1000" 0 150 39 H V C CNN +F2 "" 0 0 39 H V C CNN +F3 "" 0 0 39 H V C CNN +DRAW +S -350 100 350 -150 0 1 0 N +X +VIN 1 -550 0 197 R 50 50 1 1 I +X GND 2 0 -350 197 U 50 50 1 1 I +X +VOUT 3 550 0 197 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Custom-Parts/power_reg.pretty/VXO7803-1000.kicad_mod b/Custom-Parts/power_reg.pretty/VXO7803-1000.kicad_mod new file mode 100644 index 0000000..cbd5ac2 --- /dev/null +++ b/Custom-Parts/power_reg.pretty/VXO7803-1000.kicad_mod @@ -0,0 +1,16 @@ +(module VXO7803-1000 (layer F.Cu) (tedit 5B469556) + (fp_text reference REF** (at 0 5.715) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value VXO7803-1000 (at 0 -1.8) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -5.8 -1) (end 0 -1) (layer F.SilkS) (width 0.15)) + (fp_line (start -5.8 6.5) (end -5.8 -1) (layer F.SilkS) (width 0.15)) + (fp_line (start 5.8 6.5) (end -5.8 6.5) (layer F.SilkS) (width 0.15)) + (fp_line (start 5.8 -1) (end 5.8 6.5) (layer F.SilkS) (width 0.15)) + (fp_line (start 0 -1) (end 5.8 -1) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole circle (at 2.54 0) (size 1.7 1.7) (drill 1.2) (layers *.Cu *.Mask F.SilkS)) + (pad 2 thru_hole circle (at 0 0) (size 1.7 1.7) (drill 1.2) (layers *.Cu *.Mask F.SilkS)) + (pad 3 thru_hole circle (at -2.54 0) (size 1.7 1.7) (drill 1.2) (layers *.Cu *.Mask F.SilkS)) +)