# Memory Description and Overview

Unfortunately, the ECP5-45k doesn't have a particularly large amount of memory,
so we may need to get fancy if we want decent performance.

We only have 108 19kbit EBRs. In order to sample at full rate, we need enough memory to hold all 2ms
of our sample data. The maximum configuration we can do, while actually having reasoable resources left
over for the rest of the design, is 20MHz @ 9bits/sample, which would take 20EBR blocks per channel.
(40,000 samples, 20 EBRs gives us max 40,960 samples). This would leave us 28 EBR blocks,
or approximately 48KiB of EBR left. Most of this will likely need to be used for cache and other
resources in LiteETH and LiteDRAM.

Generating an example LiteX config with LiteETH and LiteDRAM uses 53 (!!!) EBRs.

LiteETH uses 10
LiteDRAM uses 18

Looks like I'm going to have to back down to 10MHz @ 9bits. Unfortunate, but whatever.

This leaves me with 68 EBRs to play with. I need 10 for LiteETH, so 58 for
system memory and other usages.  This may be able to fit the firmware. The
actual amount of business logic I need to fit there is surprisingly small. If it
can't, I may need to add a LiteDRAM instance, add some CPU icache and dcache,
add some DMA and a SPI flash controller to copy the code into DRAM. This will
come at the cost of some performance, and be extra work, but if I have to I have
to.

Everything will just live on a unified memory bus. I'll have one arbiter
handling all initiators and one decoder splitting up the address space.
