//--------------------------------------------------------------------------------
// Auto-generated by LiteX (8159b5ca) on 2023-02-07 21:33:18
//--------------------------------------------------------------------------------
#include <generated/soc.h>
#ifndef __GENERATED_CSR_H
#define __GENERATED_CSR_H
#include <stdint.h>
#include <system.h>
#ifndef CSR_ACCESSORS_DEFINED
#include <hw/common.h>
#endif /* ! CSR_ACCESSORS_DEFINED */
#ifndef CSR_BASE
#define CSR_BASE 0x0L
#endif

/* ctrl */
#define CSR_CTRL_BASE (CSR_BASE + 0x0L)
#define CSR_CTRL_RESET_ADDR (CSR_BASE + 0x0L)
#define CSR_CTRL_RESET_SIZE 1
static inline uint32_t ctrl_reset_read(void) {
	return csr_read_simple((CSR_BASE + 0x0L));
}
static inline void ctrl_reset_write(uint32_t v) {
	csr_write_simple(v, (CSR_BASE + 0x0L));
}
#define CSR_CTRL_RESET_SOC_RST_OFFSET 0
#define CSR_CTRL_RESET_SOC_RST_SIZE 1
static inline uint32_t ctrl_reset_soc_rst_extract(uint32_t oldword) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return ( (oldword >> 0) & mask );
}
static inline uint32_t ctrl_reset_soc_rst_read(void) {
	uint32_t word = ctrl_reset_read();
	return ctrl_reset_soc_rst_extract(word);
}
static inline uint32_t ctrl_reset_soc_rst_replace(uint32_t oldword, uint32_t plain_value) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void ctrl_reset_soc_rst_write(uint32_t plain_value) {
	uint32_t oldword = ctrl_reset_read();
	uint32_t newword = ctrl_reset_soc_rst_replace(oldword, plain_value);
	ctrl_reset_write(newword);
}
#define CSR_CTRL_RESET_CPU_RST_OFFSET 1
#define CSR_CTRL_RESET_CPU_RST_SIZE 1
static inline uint32_t ctrl_reset_cpu_rst_extract(uint32_t oldword) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return ( (oldword >> 1) & mask );
}
static inline uint32_t ctrl_reset_cpu_rst_read(void) {
	uint32_t word = ctrl_reset_read();
	return ctrl_reset_cpu_rst_extract(word);
}
static inline uint32_t ctrl_reset_cpu_rst_replace(uint32_t oldword, uint32_t plain_value) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void ctrl_reset_cpu_rst_write(uint32_t plain_value) {
	uint32_t oldword = ctrl_reset_read();
	uint32_t newword = ctrl_reset_cpu_rst_replace(oldword, plain_value);
	ctrl_reset_write(newword);
}
#define CSR_CTRL_SCRATCH_ADDR (CSR_BASE + 0x4L)
#define CSR_CTRL_SCRATCH_SIZE 1
static inline uint32_t ctrl_scratch_read(void) {
	return csr_read_simple((CSR_BASE + 0x4L));
}
static inline void ctrl_scratch_write(uint32_t v) {
	csr_write_simple(v, (CSR_BASE + 0x4L));
}
#define CSR_CTRL_BUS_ERRORS_ADDR (CSR_BASE + 0x8L)
#define CSR_CTRL_BUS_ERRORS_SIZE 1
static inline uint32_t ctrl_bus_errors_read(void) {
	return csr_read_simple((CSR_BASE + 0x8L));
}

/* ethmac */
#define CSR_ETHMAC_BASE (CSR_BASE + 0x800L)
#define CSR_ETHMAC_SRAM_WRITER_SLOT_ADDR (CSR_BASE + 0x800L)
#define CSR_ETHMAC_SRAM_WRITER_SLOT_SIZE 1
static inline uint32_t ethmac_sram_writer_slot_read(void) {
	return csr_read_simple((CSR_BASE + 0x800L));
}
#define CSR_ETHMAC_SRAM_WRITER_LENGTH_ADDR (CSR_BASE + 0x804L)
#define CSR_ETHMAC_SRAM_WRITER_LENGTH_SIZE 1
static inline uint32_t ethmac_sram_writer_length_read(void) {
	return csr_read_simple((CSR_BASE + 0x804L));
}
#define CSR_ETHMAC_SRAM_WRITER_ERRORS_ADDR (CSR_BASE + 0x808L)
#define CSR_ETHMAC_SRAM_WRITER_ERRORS_SIZE 1
static inline uint32_t ethmac_sram_writer_errors_read(void) {
	return csr_read_simple((CSR_BASE + 0x808L));
}
#define CSR_ETHMAC_SRAM_WRITER_EV_STATUS_ADDR (CSR_BASE + 0x80cL)
#define CSR_ETHMAC_SRAM_WRITER_EV_STATUS_SIZE 1
static inline uint32_t ethmac_sram_writer_ev_status_read(void) {
	return csr_read_simple((CSR_BASE + 0x80cL));
}
#define CSR_ETHMAC_SRAM_WRITER_EV_STATUS_AVAILABLE_OFFSET 0
#define CSR_ETHMAC_SRAM_WRITER_EV_STATUS_AVAILABLE_SIZE 1
static inline uint32_t ethmac_sram_writer_ev_status_available_extract(uint32_t oldword) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return ( (oldword >> 0) & mask );
}
static inline uint32_t ethmac_sram_writer_ev_status_available_read(void) {
	uint32_t word = ethmac_sram_writer_ev_status_read();
	return ethmac_sram_writer_ev_status_available_extract(word);
}
#define CSR_ETHMAC_SRAM_WRITER_EV_PENDING_ADDR (CSR_BASE + 0x810L)
#define CSR_ETHMAC_SRAM_WRITER_EV_PENDING_SIZE 1
static inline uint32_t ethmac_sram_writer_ev_pending_read(void) {
	return csr_read_simple((CSR_BASE + 0x810L));
}
static inline void ethmac_sram_writer_ev_pending_write(uint32_t v) {
	csr_write_simple(v, (CSR_BASE + 0x810L));
}
#define CSR_ETHMAC_SRAM_WRITER_EV_PENDING_AVAILABLE_OFFSET 0
#define CSR_ETHMAC_SRAM_WRITER_EV_PENDING_AVAILABLE_SIZE 1
static inline uint32_t ethmac_sram_writer_ev_pending_available_extract(uint32_t oldword) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return ( (oldword >> 0) & mask );
}
static inline uint32_t ethmac_sram_writer_ev_pending_available_read(void) {
	uint32_t word = ethmac_sram_writer_ev_pending_read();
	return ethmac_sram_writer_ev_pending_available_extract(word);
}
static inline uint32_t ethmac_sram_writer_ev_pending_available_replace(uint32_t oldword, uint32_t plain_value) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void ethmac_sram_writer_ev_pending_available_write(uint32_t plain_value) {
	uint32_t oldword = ethmac_sram_writer_ev_pending_read();
	uint32_t newword = ethmac_sram_writer_ev_pending_available_replace(oldword, plain_value);
	ethmac_sram_writer_ev_pending_write(newword);
}
#define CSR_ETHMAC_SRAM_WRITER_EV_ENABLE_ADDR (CSR_BASE + 0x814L)
#define CSR_ETHMAC_SRAM_WRITER_EV_ENABLE_SIZE 1
static inline uint32_t ethmac_sram_writer_ev_enable_read(void) {
	return csr_read_simple((CSR_BASE + 0x814L));
}
static inline void ethmac_sram_writer_ev_enable_write(uint32_t v) {
	csr_write_simple(v, (CSR_BASE + 0x814L));
}
#define CSR_ETHMAC_SRAM_WRITER_EV_ENABLE_AVAILABLE_OFFSET 0
#define CSR_ETHMAC_SRAM_WRITER_EV_ENABLE_AVAILABLE_SIZE 1
static inline uint32_t ethmac_sram_writer_ev_enable_available_extract(uint32_t oldword) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return ( (oldword >> 0) & mask );
}
static inline uint32_t ethmac_sram_writer_ev_enable_available_read(void) {
	uint32_t word = ethmac_sram_writer_ev_enable_read();
	return ethmac_sram_writer_ev_enable_available_extract(word);
}
static inline uint32_t ethmac_sram_writer_ev_enable_available_replace(uint32_t oldword, uint32_t plain_value) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void ethmac_sram_writer_ev_enable_available_write(uint32_t plain_value) {
	uint32_t oldword = ethmac_sram_writer_ev_enable_read();
	uint32_t newword = ethmac_sram_writer_ev_enable_available_replace(oldword, plain_value);
	ethmac_sram_writer_ev_enable_write(newword);
}
#define CSR_ETHMAC_SRAM_READER_START_ADDR (CSR_BASE + 0x818L)
#define CSR_ETHMAC_SRAM_READER_START_SIZE 1
static inline uint32_t ethmac_sram_reader_start_read(void) {
	return csr_read_simple((CSR_BASE + 0x818L));
}
static inline void ethmac_sram_reader_start_write(uint32_t v) {
	csr_write_simple(v, (CSR_BASE + 0x818L));
}
#define CSR_ETHMAC_SRAM_READER_READY_ADDR (CSR_BASE + 0x81cL)
#define CSR_ETHMAC_SRAM_READER_READY_SIZE 1
static inline uint32_t ethmac_sram_reader_ready_read(void) {
	return csr_read_simple((CSR_BASE + 0x81cL));
}
#define CSR_ETHMAC_SRAM_READER_LEVEL_ADDR (CSR_BASE + 0x820L)
#define CSR_ETHMAC_SRAM_READER_LEVEL_SIZE 1
static inline uint32_t ethmac_sram_reader_level_read(void) {
	return csr_read_simple((CSR_BASE + 0x820L));
}
#define CSR_ETHMAC_SRAM_READER_SLOT_ADDR (CSR_BASE + 0x824L)
#define CSR_ETHMAC_SRAM_READER_SLOT_SIZE 1
static inline uint32_t ethmac_sram_reader_slot_read(void) {
	return csr_read_simple((CSR_BASE + 0x824L));
}
static inline void ethmac_sram_reader_slot_write(uint32_t v) {
	csr_write_simple(v, (CSR_BASE + 0x824L));
}
#define CSR_ETHMAC_SRAM_READER_LENGTH_ADDR (CSR_BASE + 0x828L)
#define CSR_ETHMAC_SRAM_READER_LENGTH_SIZE 1
static inline uint32_t ethmac_sram_reader_length_read(void) {
	return csr_read_simple((CSR_BASE + 0x828L));
}
static inline void ethmac_sram_reader_length_write(uint32_t v) {
	csr_write_simple(v, (CSR_BASE + 0x828L));
}
#define CSR_ETHMAC_SRAM_READER_EV_STATUS_ADDR (CSR_BASE + 0x82cL)
#define CSR_ETHMAC_SRAM_READER_EV_STATUS_SIZE 1
static inline uint32_t ethmac_sram_reader_ev_status_read(void) {
	return csr_read_simple((CSR_BASE + 0x82cL));
}
#define CSR_ETHMAC_SRAM_READER_EV_STATUS_EVENT0_OFFSET 0
#define CSR_ETHMAC_SRAM_READER_EV_STATUS_EVENT0_SIZE 1
static inline uint32_t ethmac_sram_reader_ev_status_event0_extract(uint32_t oldword) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return ( (oldword >> 0) & mask );
}
static inline uint32_t ethmac_sram_reader_ev_status_event0_read(void) {
	uint32_t word = ethmac_sram_reader_ev_status_read();
	return ethmac_sram_reader_ev_status_event0_extract(word);
}
#define CSR_ETHMAC_SRAM_READER_EV_PENDING_ADDR (CSR_BASE + 0x830L)
#define CSR_ETHMAC_SRAM_READER_EV_PENDING_SIZE 1
static inline uint32_t ethmac_sram_reader_ev_pending_read(void) {
	return csr_read_simple((CSR_BASE + 0x830L));
}
static inline void ethmac_sram_reader_ev_pending_write(uint32_t v) {
	csr_write_simple(v, (CSR_BASE + 0x830L));
}
#define CSR_ETHMAC_SRAM_READER_EV_PENDING_EVENT0_OFFSET 0
#define CSR_ETHMAC_SRAM_READER_EV_PENDING_EVENT0_SIZE 1
static inline uint32_t ethmac_sram_reader_ev_pending_event0_extract(uint32_t oldword) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return ( (oldword >> 0) & mask );
}
static inline uint32_t ethmac_sram_reader_ev_pending_event0_read(void) {
	uint32_t word = ethmac_sram_reader_ev_pending_read();
	return ethmac_sram_reader_ev_pending_event0_extract(word);
}
static inline uint32_t ethmac_sram_reader_ev_pending_event0_replace(uint32_t oldword, uint32_t plain_value) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void ethmac_sram_reader_ev_pending_event0_write(uint32_t plain_value) {
	uint32_t oldword = ethmac_sram_reader_ev_pending_read();
	uint32_t newword = ethmac_sram_reader_ev_pending_event0_replace(oldword, plain_value);
	ethmac_sram_reader_ev_pending_write(newword);
}
#define CSR_ETHMAC_SRAM_READER_EV_ENABLE_ADDR (CSR_BASE + 0x834L)
#define CSR_ETHMAC_SRAM_READER_EV_ENABLE_SIZE 1
static inline uint32_t ethmac_sram_reader_ev_enable_read(void) {
	return csr_read_simple((CSR_BASE + 0x834L));
}
static inline void ethmac_sram_reader_ev_enable_write(uint32_t v) {
	csr_write_simple(v, (CSR_BASE + 0x834L));
}
#define CSR_ETHMAC_SRAM_READER_EV_ENABLE_EVENT0_OFFSET 0
#define CSR_ETHMAC_SRAM_READER_EV_ENABLE_EVENT0_SIZE 1
static inline uint32_t ethmac_sram_reader_ev_enable_event0_extract(uint32_t oldword) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return ( (oldword >> 0) & mask );
}
static inline uint32_t ethmac_sram_reader_ev_enable_event0_read(void) {
	uint32_t word = ethmac_sram_reader_ev_enable_read();
	return ethmac_sram_reader_ev_enable_event0_extract(word);
}
static inline uint32_t ethmac_sram_reader_ev_enable_event0_replace(uint32_t oldword, uint32_t plain_value) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void ethmac_sram_reader_ev_enable_event0_write(uint32_t plain_value) {
	uint32_t oldword = ethmac_sram_reader_ev_enable_read();
	uint32_t newword = ethmac_sram_reader_ev_enable_event0_replace(oldword, plain_value);
	ethmac_sram_reader_ev_enable_write(newword);
}
#define CSR_ETHMAC_PREAMBLE_CRC_ADDR (CSR_BASE + 0x838L)
#define CSR_ETHMAC_PREAMBLE_CRC_SIZE 1
static inline uint32_t ethmac_preamble_crc_read(void) {
	return csr_read_simple((CSR_BASE + 0x838L));
}
#define CSR_ETHMAC_RX_DATAPATH_PREAMBLE_ERRORS_ADDR (CSR_BASE + 0x83cL)
#define CSR_ETHMAC_RX_DATAPATH_PREAMBLE_ERRORS_SIZE 1
static inline uint32_t ethmac_rx_datapath_preamble_errors_read(void) {
	return csr_read_simple((CSR_BASE + 0x83cL));
}
#define CSR_ETHMAC_RX_DATAPATH_CRC_ERRORS_ADDR (CSR_BASE + 0x840L)
#define CSR_ETHMAC_RX_DATAPATH_CRC_ERRORS_SIZE 1
static inline uint32_t ethmac_rx_datapath_crc_errors_read(void) {
	return csr_read_simple((CSR_BASE + 0x840L));
}

/* ethphy */
#define CSR_ETHPHY_BASE (CSR_BASE + 0x1000L)
#define CSR_ETHPHY_CRG_RESET_ADDR (CSR_BASE + 0x1000L)
#define CSR_ETHPHY_CRG_RESET_SIZE 1
static inline uint32_t ethphy_crg_reset_read(void) {
	return csr_read_simple((CSR_BASE + 0x1000L));
}
static inline void ethphy_crg_reset_write(uint32_t v) {
	csr_write_simple(v, (CSR_BASE + 0x1000L));
}
#define CSR_ETHPHY_RX_INBAND_STATUS_ADDR (CSR_BASE + 0x1004L)
#define CSR_ETHPHY_RX_INBAND_STATUS_SIZE 1
static inline uint32_t ethphy_rx_inband_status_read(void) {
	return csr_read_simple((CSR_BASE + 0x1004L));
}
#define CSR_ETHPHY_RX_INBAND_STATUS_LINK_STATUS_OFFSET 0
#define CSR_ETHPHY_RX_INBAND_STATUS_LINK_STATUS_SIZE 1
static inline uint32_t ethphy_rx_inband_status_link_status_extract(uint32_t oldword) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return ( (oldword >> 0) & mask );
}
static inline uint32_t ethphy_rx_inband_status_link_status_read(void) {
	uint32_t word = ethphy_rx_inband_status_read();
	return ethphy_rx_inband_status_link_status_extract(word);
}
#define CSR_ETHPHY_RX_INBAND_STATUS_CLOCK_SPEED_OFFSET 1
#define CSR_ETHPHY_RX_INBAND_STATUS_CLOCK_SPEED_SIZE 1
static inline uint32_t ethphy_rx_inband_status_clock_speed_extract(uint32_t oldword) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return ( (oldword >> 1) & mask );
}
static inline uint32_t ethphy_rx_inband_status_clock_speed_read(void) {
	uint32_t word = ethphy_rx_inband_status_read();
	return ethphy_rx_inband_status_clock_speed_extract(word);
}
#define CSR_ETHPHY_RX_INBAND_STATUS_DUPLEX_STATUS_OFFSET 2
#define CSR_ETHPHY_RX_INBAND_STATUS_DUPLEX_STATUS_SIZE 1
static inline uint32_t ethphy_rx_inband_status_duplex_status_extract(uint32_t oldword) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return ( (oldword >> 2) & mask );
}
static inline uint32_t ethphy_rx_inband_status_duplex_status_read(void) {
	uint32_t word = ethphy_rx_inband_status_read();
	return ethphy_rx_inband_status_duplex_status_extract(word);
}
#define CSR_ETHPHY_MDIO_W_ADDR (CSR_BASE + 0x1008L)
#define CSR_ETHPHY_MDIO_W_SIZE 1
static inline uint32_t ethphy_mdio_w_read(void) {
	return csr_read_simple((CSR_BASE + 0x1008L));
}
static inline void ethphy_mdio_w_write(uint32_t v) {
	csr_write_simple(v, (CSR_BASE + 0x1008L));
}
#define CSR_ETHPHY_MDIO_W_MDC_OFFSET 0
#define CSR_ETHPHY_MDIO_W_MDC_SIZE 1
static inline uint32_t ethphy_mdio_w_mdc_extract(uint32_t oldword) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return ( (oldword >> 0) & mask );
}
static inline uint32_t ethphy_mdio_w_mdc_read(void) {
	uint32_t word = ethphy_mdio_w_read();
	return ethphy_mdio_w_mdc_extract(word);
}
static inline uint32_t ethphy_mdio_w_mdc_replace(uint32_t oldword, uint32_t plain_value) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void ethphy_mdio_w_mdc_write(uint32_t plain_value) {
	uint32_t oldword = ethphy_mdio_w_read();
	uint32_t newword = ethphy_mdio_w_mdc_replace(oldword, plain_value);
	ethphy_mdio_w_write(newword);
}
#define CSR_ETHPHY_MDIO_W_OE_OFFSET 1
#define CSR_ETHPHY_MDIO_W_OE_SIZE 1
static inline uint32_t ethphy_mdio_w_oe_extract(uint32_t oldword) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return ( (oldword >> 1) & mask );
}
static inline uint32_t ethphy_mdio_w_oe_read(void) {
	uint32_t word = ethphy_mdio_w_read();
	return ethphy_mdio_w_oe_extract(word);
}
static inline uint32_t ethphy_mdio_w_oe_replace(uint32_t oldword, uint32_t plain_value) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void ethphy_mdio_w_oe_write(uint32_t plain_value) {
	uint32_t oldword = ethphy_mdio_w_read();
	uint32_t newword = ethphy_mdio_w_oe_replace(oldword, plain_value);
	ethphy_mdio_w_write(newword);
}
#define CSR_ETHPHY_MDIO_W_W_OFFSET 2
#define CSR_ETHPHY_MDIO_W_W_SIZE 1
static inline uint32_t ethphy_mdio_w_w_extract(uint32_t oldword) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return ( (oldword >> 2) & mask );
}
static inline uint32_t ethphy_mdio_w_w_read(void) {
	uint32_t word = ethphy_mdio_w_read();
	return ethphy_mdio_w_w_extract(word);
}
static inline uint32_t ethphy_mdio_w_w_replace(uint32_t oldword, uint32_t plain_value) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return (oldword & (~(mask << 2))) | (mask & plain_value)<< 2 ;
}
static inline void ethphy_mdio_w_w_write(uint32_t plain_value) {
	uint32_t oldword = ethphy_mdio_w_read();
	uint32_t newword = ethphy_mdio_w_w_replace(oldword, plain_value);
	ethphy_mdio_w_write(newword);
}
#define CSR_ETHPHY_MDIO_R_ADDR (CSR_BASE + 0x100cL)
#define CSR_ETHPHY_MDIO_R_SIZE 1
static inline uint32_t ethphy_mdio_r_read(void) {
	return csr_read_simple((CSR_BASE + 0x100cL));
}
#define CSR_ETHPHY_MDIO_R_R_OFFSET 0
#define CSR_ETHPHY_MDIO_R_R_SIZE 1
static inline uint32_t ethphy_mdio_r_r_extract(uint32_t oldword) {
	uint32_t mask = ((uint32_t)(1 << 1)-1);
	return ( (oldword >> 0) & mask );
}
static inline uint32_t ethphy_mdio_r_r_read(void) {
	uint32_t word = ethphy_mdio_r_read();
	return ethphy_mdio_r_r_extract(word);
}

#endif
