from amaranth import *
from amaranth_soc.wishbone import *
from amaranth_soc.memory import *
from math import ceil, log2

class TimerPeripheral(Elaboratable, Interface):
    def __init__(self, clock_freq: int, wanted_freq: int):
        Interface.__init__(self, addr_width=1, data_width=32, granularity=8)
        memory_map = MemoryMap(addr_width=3, data_width=8)
        self.memory_map = memory_map

        self.ratio = ceil(clock_freq / wanted_freq)

    def elaborate(self, platform):
        m = Module()

        counter = Signal(ceil(log2(self.ratio)))
        value = Signal(32)

        # Up count
        m.d.sync += counter.eq(counter + 1)

        # Divider value reached, increment
        with m.If(counter >= self.ratio):
            m.d.sync += [
                value.eq(value + 1),
                counter.eq(0),
            ]

        m.d.sync += self.ack.eq(0)
        with m.If(self.cyc & self.stb):
            m.d.sync += [
                self.ack.eq(1),
                self.dat_r.eq(value),
            ]

        return m