From 1b39199df3b05c42647409b6468111ac2c2c1261 Mon Sep 17 00:00:00 2001
From: David Lenfesty <lenfesty@ualberta.ca>
Date: Sat, 25 Feb 2023 12:24:03 -0700
Subject: [PATCH] gateware: generate PLL with 'ecppll'

---
 gateware/gen_pll.sh |  3 +++
 gateware/pll.v      | 53 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+)
 create mode 100755 gateware/gen_pll.sh
 create mode 100644 gateware/pll.v

diff --git a/gateware/gen_pll.sh b/gateware/gen_pll.sh
new file mode 100755
index 0000000..7ecd9f0
--- /dev/null
+++ b/gateware/gen_pll.sh
@@ -0,0 +1,3 @@
+#!/usr/bin/env sh
+
+ecppll --clkin 25 --clkout0 50 --clkout1 10 -f pll.v
\ No newline at end of file
diff --git a/gateware/pll.v b/gateware/pll.v
new file mode 100644
index 0000000..3afe677
--- /dev/null
+++ b/gateware/pll.v
@@ -0,0 +1,53 @@
+// diamond 3.7 accepts this PLL
+// diamond 3.8-3.9 is untested
+// diamond 3.10 or higher is likely to abort with error about unable to use feedback signal
+// cause of this could be from wrong CPHASE/FPHASE parameters
+module pll
+(
+    input clkin, // 25 MHz, 0 deg
+    output clkout0, // 50 MHz, 0 deg
+    output clkout1, // 10 MHz, 0 deg
+    output locked
+);
+(* FREQUENCY_PIN_CLKI="25" *)
+(* FREQUENCY_PIN_CLKOP="50" *)
+(* FREQUENCY_PIN_CLKOS="10" *)
+(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
+EHXPLLL #(
+        .PLLRST_ENA("DISABLED"),
+        .INTFB_WAKE("DISABLED"),
+        .STDBY_ENABLE("DISABLED"),
+        .DPHASE_SOURCE("DISABLED"),
+        .OUTDIVIDER_MUXA("DIVA"),
+        .OUTDIVIDER_MUXB("DIVB"),
+        .OUTDIVIDER_MUXC("DIVC"),
+        .OUTDIVIDER_MUXD("DIVD"),
+        .CLKI_DIV(1),
+        .CLKOP_ENABLE("ENABLED"),
+        .CLKOP_DIV(12),
+        .CLKOP_CPHASE(5),
+        .CLKOP_FPHASE(0),
+        .CLKOS_ENABLE("ENABLED"),
+        .CLKOS_DIV(60),
+        .CLKOS_CPHASE(5),
+        .CLKOS_FPHASE(0),
+        .FEEDBK_PATH("CLKOP"),
+        .CLKFB_DIV(2)
+    ) pll_i (
+        .RST(1'b0),
+        .STDBY(1'b0),
+        .CLKI(clkin),
+        .CLKOP(clkout0),
+        .CLKOS(clkout1),
+        .CLKFB(clkout0),
+        .CLKINTFB(),
+        .PHASESEL0(1'b0),
+        .PHASESEL1(1'b0),
+        .PHASEDIR(1'b1),
+        .PHASESTEP(1'b1),
+        .PHASELOADREG(1'b1),
+        .PLLWAKESYNC(1'b0),
+        .ENCLKOP(1'b0),
+        .LOCK(locked)
+	);
+endmodule