diff --git a/gateware/memory.py b/gateware/memory.py
index 5bde3ea..d512a8c 100644
--- a/gateware/memory.py
+++ b/gateware/memory.py
@@ -57,6 +57,7 @@ class ROM(Elaboratable, Interface):
 class RAM(Elaboratable, Interface):
     def __init__(self, *, size_bytes=4096):
         addr_width = ceil(log2(size_bytes >> 2))
+        self.addr_width = addr_width
         self.data = Memory(width=32, depth=size_bytes >> 2)
         self.r = self.data.read_port()
         self.w = self.data.write_port()
@@ -81,6 +82,19 @@ class RAM(Elaboratable, Interface):
         m.submodules.r = self.r
         m.submodules.w = self.w
 
+        # TODO not sure if this is the idiomatic way
+        self.r.en = Const(1)
+        # Default to not writing data
+        m.d.sync += self.w.en.eq(0)
+
+
+        # Use read data to populate un-written wishbone data for sub-32-bit reads
+        for i in range(4):
+            with m.If(self.sel.bit_select(i, 1)):
+                m.d.sync += self.w.data.word_select(i, 8).eq(self.dat_w.word_select(i, 8))
+            with m.Else():
+                m.d.sync += self.w.data.word_select(i, 8).eq(self.r.data.word_select(i, 8))
+
         # 'ack' signal should rest at 0.
         m.d.sync += self.ack.eq(0)
         # Simulated reads only take one cycle, but only acknowledge
@@ -98,7 +112,7 @@ class RAM(Elaboratable, Interface):
             self.r.addr.eq( self.adr ),
             self.dat_r.eq( self.r.data ),
             self.w.addr.eq(self.adr),
-            self.w.data.eq(self.dat_w),
+            #self.w.data.eq(self.dat_w),
         ]
 
         # End of simulated memory module.