From 29ec5a8a43d9ed805bb3803df606529701ff62f7 Mon Sep 17 00:00:00 2001
From: David Lenfesty <lenfesty@ualberta.ca>
Date: Sun, 16 Apr 2023 11:06:02 -0600
Subject: [PATCH] tracking a couple files I missed

---
 firmware/src/logging.rs | 38 ++++++++++++++++++++++++++++++++++++++
 gateware/timer.py       | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 75 insertions(+)
 create mode 100644 firmware/src/logging.rs
 create mode 100644 gateware/timer.py

diff --git a/firmware/src/logging.rs b/firmware/src/logging.rs
new file mode 100644
index 0000000..940fd4e
--- /dev/null
+++ b/firmware/src/logging.rs
@@ -0,0 +1,38 @@
+use core::{fmt::Write, any::Any};
+
+use defmt;
+
+use crate::uart::AmlibUart;
+use core::arch::asm;
+
+#[defmt::global_logger]
+struct DefmtLogger;
+
+unsafe impl defmt::Logger for DefmtLogger {
+    fn acquire() {
+        // Sync methods left empty because we don't use any interrupts
+    }
+
+    unsafe fn flush() {
+        // Sync methods left empty because we don't use any interrupts
+    }
+
+    unsafe fn release() {
+        // Sync methods left empty because we don't use any interrupts
+    }
+
+    unsafe fn write(bytes: &[u8]) {
+        static mut UART: Option<AmlibUart> = None;
+        if UART.is_none() {
+            UART = Some(AmlibUart::new(0x0200_0040));
+        }
+
+
+        let mut dev = UART.unwrap();
+        //writeln!(dev, "a").unwrap();
+        //writeln!(dev, "length: {}", bytes.len());
+        for byte in bytes {
+            while let Err(_) = dev.try_put_char(*byte) {}
+        }
+    }
+}
diff --git a/gateware/timer.py b/gateware/timer.py
new file mode 100644
index 0000000..337f85f
--- /dev/null
+++ b/gateware/timer.py
@@ -0,0 +1,37 @@
+from amaranth import *
+from amaranth_soc.wishbone import *
+from amaranth_soc.memory import *
+from math import ceil, log2
+
+class TimerPeripheral(Elaboratable, Interface):
+    def __init__(self, clock_freq: int, wanted_freq: int):
+        Interface.__init__(self, addr_width=1, data_width=32, granularity=8)
+        memory_map = MemoryMap(addr_width=3, data_width=8)
+        self.memory_map = memory_map
+
+        self.ratio = ceil(clock_freq / wanted_freq)
+
+    def elaborate(self, platform):
+        m = Module()
+
+        counter = Signal(ceil(log2(self.ratio)))
+        value = Signal(32)
+
+        # Up count
+        m.d.sync += counter.eq(counter + 1)
+
+        # Divider value reached, increment
+        with m.If(counter >= self.ratio):
+            m.d.sync += [
+                value.eq(value + 1),
+                counter.eq(0),
+            ]
+
+        m.d.sync += self.ack.eq(0)
+        with m.If(self.cyc & self.stb):
+            m.d.sync += [
+                self.ack.eq(1),
+                self.dat_r.eq(value),
+            ]
+
+        return m
\ No newline at end of file