gateware: fix sizing and add size configurability
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@ -122,7 +122,7 @@ class Core(Elaboratable):
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fw = load_firmware_for_mem()
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# Hook up memory space
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self.rom = ROM(fw)
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self.rom = ROM(size_bytes=8192, data=fw)
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m.submodules.rom = self.rom
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# Problem: not sure to handle how we do byte vs word addressing properly
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# So doing this shift is a bit of a hacky way to impl anything
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@ -2,25 +2,28 @@ from amaranth import *
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from amaranth_soc.wishbone import *
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from amaranth_soc.memory import *
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from math import log2, ceil
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# TODO impl select
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# We sub-class wishbone.Interface here because it needs to be a bus object to be added as a window to Wishbone stuff
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class ROM(Elaboratable, Interface):
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def __init__(self, data=None):
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def __init__(self, *, size_bytes=4096, data=None):
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#self.size = len(data)
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self.data = Memory(width=32, depth=(4096 >> 2), init=data)
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addr_width = ceil(log2(size_bytes >> 2))
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self.data = Memory(width=32, depth=size_bytes >> 2, init=data)
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self.r = self.data.read_port()
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# Need to init Interface
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Interface.__init__(self, addr_width=10, data_width=32, granularity=8)
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Interface.__init__(self, addr_width=addr_width, data_width=32, granularity=8)
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# This is effectively a "window", and it has a certain set of resources
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# 12 = log2(4096)
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memory_map = MemoryMap(addr_width=12, data_width=8)
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memory_map = MemoryMap(addr_width=addr_width + 2, data_width=8)
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# TODO need to unify how I deal with size
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# In this case, one resource, which is out memory
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memory_map.add_resource(self.data, name="rom_data", size=(4096 >> 2))
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memory_map.add_resource(self.data, name="rom_data", size=size_bytes)
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self.memory_map = memory_map
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@ -52,21 +55,21 @@ class ROM(Elaboratable, Interface):
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# TODO support read segmentation or whatever it's called, where you read/write certian bytes from memory
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# Otherwise we can't store individual bytes, and this will wreck shit in weird ways.
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class RAM(Elaboratable, Interface):
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def __init__(self):
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#self.size = len(data)
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self.data = Memory(width=32, depth=(4096 >> 2))
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def __init__(self, *, size_bytes=4096):
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addr_width = ceil(log2(size_bytes >> 2))
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self.data = Memory(width=32, depth=size_bytes >> 2)
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self.r = self.data.read_port()
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self.w = self.data.write_port()
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# Need to init Interface
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Interface.__init__(self, addr_width=10, data_width=32, granularity=8)
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Interface.__init__(self, addr_width=addr_width, data_width=32, granularity=8)
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# This is effectively a "window", and it has a certain set of resources
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# 12 = log2(4096)
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memory_map = MemoryMap(addr_width=12, data_width=8)
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memory_map = MemoryMap(addr_width=addr_width + 2, data_width=8)
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# TODO need to unify how I deal with size
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# In this case, one resource, which is out memory
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memory_map.add_resource(self.data, name="ram_data", size=(4096 >> 2))
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memory_map.add_resource(self.data, name="ram_data", size=size_bytes)
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self.memory_map = memory_map
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