fw: start debug i2c
This commit is contained in:
parent
c1c0122684
commit
349fe96b0d
@ -36,7 +36,7 @@ const NUM_TX_SLOTS: u32 = 2;
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const MTU: usize = 1530;
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const SLOT_LEN: u32 = 2048;
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use crate::{busy_wait, read_reg, write_reg};
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use crate::{read_reg, timer::busy_wait_ms, write_reg};
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pub struct LiteEthDevice {
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csr_addr: u32,
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@ -2,146 +2,289 @@
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//!
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//! See `gateware/i2c.py` for register information
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use crate::timer::busy_wait_us;
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use crate::{read_reg, write_reg};
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use core::arch::asm;
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/// TODO repr(C) a register bank, and add instances
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// Using the blocking API because the peripheral requires fairly tight timing to operate
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// correctly, and I don't feel like writing the gateware to resolve that.
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use embedded_hal::blocking::i2c::{Read, SevenBitAddress, Write};
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use embedded_hal::blocking::i2c::{Operation, Read, SevenBitAddress, Transactional, Write};
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const CR: u32 = 0;
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const SR: u32 = 1;
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const DWR: u32 = 2;
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const DRR: u32 = 3;
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pub const BASE: u32 = 0xF000_1800;
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const REG_W: u32 = 0x00;
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const FIELD_W_SCL: u32 = 0;
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const FIELD_W_OE: u32 = 1;
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const FIELD_W_SDA: u32 = 2;
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const REG_R: u32 = 0x04;
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const FIELD_R_SDA: u32 = 0;
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const WAIT_PERIOD_US: u64 = (1_000_000 / 100_000) / 2;
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#[derive(Clone, Copy, Debug)]
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pub enum Error {
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/// Device is busy for some reason
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Busy,
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/// I2C bus returned a NACK
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Nack,
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}
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pub struct AmlibI2c {
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pub struct LitexI2c {
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base_addr: u32,
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}
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use core::fmt::Write as _;
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impl AmlibI2c {
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impl LitexI2c {
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pub fn new(base_addr: u32) -> Self {
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AmlibI2c { base_addr }
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LitexI2c { base_addr }
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}
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fn wait_while_busy(&mut self) {
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fn set_scl(&mut self, val: u32) {
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unsafe {
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while read_reg::<u8>(self.base_addr + SR) & 1 != 0 {
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asm!("nop");
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}
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write_reg(self.base_addr + REG_W, (val & 0x01) << FIELD_W_SCL);
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}
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}
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fn is_nack(&self) -> bool {
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unsafe { read_reg::<u8>(self.base_addr + SR) & 0x02 == 0 }
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fn set_sda(&mut self, val: u32) {
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unsafe {
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write_reg(self.base_addr + REG_W, (val & 0x01) << FIELD_W_SDA);
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}
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}
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fn set_oe(&mut self, val: u32) {
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unsafe {
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write_reg(self.base_addr + REG_W, (val & 0x01) << FIELD_W_OE);
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}
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}
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fn get_sda(&mut self) -> u8 {
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unsafe { read_reg::<u8>(self.base_addr + REG_R) & (1 << FIELD_R_SDA) }
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}
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/// Generate a START condition. The next operation should be a clock
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/// transition to low.
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///
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/// Assumes SCL and SDA have been high due to bus inactivity
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unsafe fn start(&mut self) {
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self.set_oe(1);
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self.set_scl(1);
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self.set_sda(1);
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busy_wait_us(WAIT_PERIOD_US);
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self.set_sda(0);
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busy_wait_us(WAIT_PERIOD_US);
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}
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/// Generate a repeated START condition.
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///
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/// Assumes it was called after an ACK bit
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unsafe fn repeated_start(&mut self) {
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self.set_scl(0);
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self.set_sda(1);
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self.set_oe(1);
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busy_wait_us(WAIT_PERIOD_US);
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self.set_scl(1);
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busy_wait_us(WAIT_PERIOD_US);
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// TODO does this third half-clock break timing?
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self.set_sda(0);
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busy_wait_us(WAIT_PERIOD_US);
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}
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/// Handles STOP conditions.
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///
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/// Assumes it was called after an ACK bit
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unsafe fn stop(&mut self) {
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self.set_scl(0);
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self.set_sda(0);
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self.set_oe(1);
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busy_wait_us(WAIT_PERIOD_US);
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self.set_scl(1);
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busy_wait_us(WAIT_PERIOD_US);
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// TODO does this third half-clock break timing?
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//self.set_oe(0); // Disable and let pullup take bus high
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self.set_sda(1);
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busy_wait_us(WAIT_PERIOD_US);
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}
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unsafe fn write_byte(&mut self, byte: u8) {
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self.set_oe(1); // Take SDA to write data out
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for i in 0..8 {
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// Write data out before we clock high
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self.set_scl(0);
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busy_wait_us(WAIT_PERIOD_US);
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// Clock data in
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self.set_scl(1);
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self.set_sda(byte as u32 >> (7 - i));
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busy_wait_us(WAIT_PERIOD_US)
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}
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}
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unsafe fn read_byte(&mut self) -> u8 {
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self.set_oe(0); // De-assert to read data
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let mut out = 0;
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for i in 0..8 {
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self.set_scl(0);
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busy_wait_us(WAIT_PERIOD_US);
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self.set_scl(1);
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busy_wait_us(WAIT_PERIOD_US);
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// TODO sampling at the end of the clock may not work 100% of the time
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// ideally should sample in the middle
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out |= (self.get_sda() << 7 - i);
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}
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out
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}
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// Returns if there was an ACK
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unsafe fn get_ack(&mut self) -> bool {
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self.set_oe(0); // Release SDA to read ACK
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self.set_sda(1);
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self.set_scl(0);
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busy_wait_us(WAIT_PERIOD_US);
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self.set_scl(1);
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busy_wait_us(WAIT_PERIOD_US);
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self.get_sda() == 0
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}
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unsafe fn set_ack(&mut self, ack: bool) {
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self.set_oe(1); // Take SDA
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self.set_sda(!ack as u32);
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self.set_scl(0);
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busy_wait_us(WAIT_PERIOD_US);
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self.set_scl(1);
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busy_wait_us(WAIT_PERIOD_US);
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}
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}
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impl Write<SevenBitAddress> for AmlibI2c {
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impl Write<SevenBitAddress> for LitexI2c {
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// TODO errors
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type Error = Error;
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fn write(&mut self, address: SevenBitAddress, bytes: &[u8]) -> Result<(), Self::Error> {
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unsafe {
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if (read_reg::<u8>(self.base_addr + SR) & 1) != 0 {
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return Err(Error::Busy);
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}
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self.start();
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// START
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write_reg(self.base_addr + CR, 0x01u8);
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self.wait_while_busy();
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// Send address byte (R/~W = 0)
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write_reg(self.base_addr + DWR, address << 1);
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write_reg(self.base_addr + CR, 0x04u8);
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self.wait_while_busy();
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// Check NACK
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if self.is_nack() {
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// Write address and write bit
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self.write_byte((address << 1) | 0);
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if !self.get_ack() {
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self.stop();
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return Err(Error::Nack);
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}
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// Write data
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for byte in bytes {
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// Write byte
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write_reg(self.base_addr + DWR, *byte);
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// Send byte
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write_reg(self.base_addr + CR, 0x04u8);
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self.wait_while_busy();
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if self.is_nack() {
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for b in bytes {
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self.write_byte(*b);
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if !self.get_ack() {
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self.stop();
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return Err(Error::Nack);
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}
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}
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// STOP
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write_reg(self.base_addr + CR, 0x02u8);
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self.stop();
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self.wait_while_busy();
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Ok(())
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}
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}
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}
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impl Read<SevenBitAddress> for AmlibI2c {
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impl Read<SevenBitAddress> for LitexI2c {
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// TODO errors
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type Error = Error;
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fn read(&mut self, address: SevenBitAddress, buffer: &mut [u8]) -> Result<(), Self::Error> {
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unsafe {
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if (read_reg::<u8>(self.base_addr + SR) & 1) != 0 {
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return Err(Error::Busy);
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}
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self.start();
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// Set read ACK to 1. Should probably ideally be done in an init() function
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// but it doesn't really matter
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write_reg(self.base_addr + CR, 0x30u8);
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// START
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write_reg(self.base_addr + CR, 0x01u8);
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self.wait_while_busy();
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// Send address byte (R/~W = 1)
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write_reg(self.base_addr + DWR, (address << 1) + 1);
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write_reg(self.base_addr + CR, 0x04u8);
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self.wait_while_busy();
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if self.is_nack() {
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self.write_byte((address << 1) | 1);
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if !self.get_ack() {
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self.stop();
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return Err(Error::Nack);
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}
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for byte in buffer {
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// Start reading in a byte
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write_reg(self.base_addr + CR, 0x08u8);
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self.wait_while_busy();
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// Value is available once busy is clear
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*byte = read_reg::<u8>(self.base_addr + DRR);
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for b in buffer {
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*b = self.read_byte();
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self.set_ack(true);
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}
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// STOP
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write_reg(self.base_addr + CR, 0x02u8);
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self.stop();
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Ok(())
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}
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}
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}
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// I don't need this for MCP4726
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//impl Transactional for AmlibI2c {
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// type Error = Error;
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//
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// fn exec<'a>(&mut self, address: u8, operations: &mut [Operation<'a>])
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// -> Result<(), Self::Error> {
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// Ok(())
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// }
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//}
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impl Transactional for LitexI2c {
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type Error = Error;
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fn exec<'a>(
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&mut self,
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address: u8,
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operations: &mut [Operation<'a>],
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) -> Result<(), Self::Error> {
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unsafe {
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let mut last_operation_was_read: Option<bool> = None;
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for op in operations {
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let op_is_read = match op {
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Operation::Write(_) => false,
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Operation::Read(_) => true,
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};
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match last_operation_was_read {
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None => {
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// First operation; send regular start and address
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self.start();
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self.write_byte((address << 1) | op_is_read as u8);
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if !self.get_ack() {
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self.stop();
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return Err(Error::Nack);
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}
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}
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Some(last_op_was_read) => {
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// Not the first, send repeated start
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self.repeated_start();
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if last_op_was_read != op_is_read {
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// Operations don't match, so we need to send address byte
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self.write_byte((address << 1) | op_is_read as u8);
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if !self.get_ack() {
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self.stop();
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return Err(Error::Nack);
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}
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}
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}
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}
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match op {
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Operation::Read(buffer) => {
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for b in buffer.iter_mut() {
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*b = self.read_byte();
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self.set_ack(true);
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}
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}
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Operation::Write(buffer) => {
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for b in buffer.iter() {
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self.write_byte(*b);
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if !self.get_ack() {
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self.stop();
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return Err(Error::Nack);
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}
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}
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}
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}
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last_operation_was_read = Some(op_is_read);
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}
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self.stop();
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}
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Ok(())
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}
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}
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@ -24,7 +24,7 @@ unsafe impl defmt::Logger for DefmtLogger {
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unsafe fn write(bytes: &[u8]) {
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static mut UART: Option<LitexUart> = None;
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if UART.is_none() {
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UART = Some(LitexUart::new(0xf000_4000));
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UART = Some(LitexUart::new(0xf000_4800));
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}
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let mut dev = UART.unwrap();
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@ -6,9 +6,7 @@
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extern crate panic_halt;
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use core::fmt::Write;
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use core::{
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ptr::{read_volatile, write_volatile},
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};
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use core::ptr::{read_volatile, write_volatile};
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use embedded_hal::prelude::{_embedded_hal_blocking_i2c_Read, _embedded_hal_blocking_i2c_Write};
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use mcp4726::Status;
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@ -30,9 +28,9 @@ mod i2c;
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mod logging;
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mod mcp4726;
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mod proto;
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mod uart;
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mod sampler;
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mod timer;
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mod uart;
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use timer::millis;
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@ -115,6 +113,9 @@ fn main() -> ! {
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let mut cmd = command_interface::CommandInterface::new();
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let mut i2c = i2c::LitexI2c::new(i2c::BASE);
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let mut dac = mcp4726::MCP4726::new(3);
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loop {
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let now = millis();
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iface.poll(Instant::from_millis(now), &mut device, &mut socket_set);
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@ -123,7 +124,7 @@ fn main() -> ! {
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cmd.run(socket_set.get_mut(command_socket));
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// TODO the need for the second check screams something is unsound somewhere
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if now - last_blink > 1000 && now > last_blink {
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if now - last_blink >= 1000 && now > last_blink {
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last_blink = now;
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toggle = !toggle;
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write_led(if toggle { 1 } else { 0 });
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@ -133,31 +134,59 @@ fn main() -> ! {
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sock.listen(3000);
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}
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if toggle {
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sampler::clear_buffers();
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sampler::start_sampling();
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defmt::debug!("heartbeat, time: {}", millis());
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let buf = unsafe {sampler::get_sample_buffer(0) };
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let status = sampler::read_status();
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let raw_reg: u32 = unsafe { read_reg(0x8040_0004) };
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defmt::debug!("Start: len: {}, complete: {}, running: {}, status: {}", buf.len(), status.capture_complete, status.sampling, raw_reg);
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} else {
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sampler::stop_sampling();
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let buf = unsafe {sampler::get_sample_buffer(0) };
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defmt::debug!("Stopped, len: {}", buf.len());
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match dac.write_config(
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&mut i2c,
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mcp4726::Config {
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vref_source: mcp4726::VRef::UnbufferedVRef,
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operation: mcp4726::PowerDown::NormalOperation,
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use_2x_gain: false,
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},
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) {
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Ok(_) => defmt::debug!("Write config success"),
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Err(_) => defmt::debug!("Write config failed"),
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}
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//match dac.read_status(&mut i2c) {
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// Ok(status) => {
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// defmt::debug!(
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// "DAC status: ready: {}, powered: {}",
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// status.ready,
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// status.device_powered
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// );
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// if sock.can_send() {
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// write!(sock, "DAC: ready: {}, powered: {}", status.ready, status.device_powered);
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// }
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// }
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// Err(_) => defmt::debug!("Error reading from DAC"),
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//};
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//if toggle {
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// sampler::clear_buffers();
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// sampler::start_sampling();
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// let buf = unsafe {sampler::get_sample_buffer(0) };
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// let status = sampler::read_status();
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// let raw_reg: u32 = unsafe { read_reg(0x8040_0004) };
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// defmt::debug!("Start: len: {}, complete: {}, running: {}, status: {}", buf.len(), status.capture_complete, status.sampling, raw_reg);
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//} else {
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// sampler::stop_sampling();
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// let buf = unsafe {sampler::get_sample_buffer(0) };
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// defmt::debug!("Stopped, len: {}", buf.len());
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//}
|
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}
|
||||
|
||||
// TODO I think the timer might actually stop until the event is cleared? this may pose
|
||||
// problems, might explain why moving this above the smoltcp stuff "broke" things
|
||||
timer::poll();
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
fn write_led(val: u32) {
|
||||
unsafe {
|
||||
write_reg(0xf000_2000, val);
|
||||
write_reg(0xf000_2800, val);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
//! Driver for custom sampler peripheral
|
||||
|
||||
use crate::{write_reg, read_reg};
|
||||
use crate::{read_reg, write_reg};
|
||||
|
||||
const BASE: u32 = 0x8040_0000;
|
||||
|
||||
|
||||
@ -3,15 +3,17 @@
|
||||
use crate::{read_reg, write_reg};
|
||||
use core::arch::asm;
|
||||
|
||||
const BASE: u32 = 0xf000_4000;
|
||||
|
||||
/// Initializes the timer to use for polling events as a wall clock.
|
||||
///
|
||||
/// Timer is running at system frequency (60MHz)
|
||||
pub fn init() {
|
||||
unsafe {
|
||||
write_reg(0xf000_3808, 0u32); // Disable timer
|
||||
write_reg(0xf000_3800, 0u32); // Set LOAD value
|
||||
write_reg(0xf000_3804, 60_000_000u32); // Set RELOAD value
|
||||
write_reg(0xf000_3808, 1u32); // Enable timer
|
||||
write_reg(BASE + 0x08, 0u32); // Disable timer
|
||||
write_reg(BASE + 0x00, 0u32); // Set LOAD value
|
||||
write_reg(BASE + 0x04, 60_000_000u32); // Set RELOAD value
|
||||
write_reg(BASE + 0x08, 1u32); // Enable timer
|
||||
}
|
||||
}
|
||||
|
||||
@ -21,13 +23,13 @@ static mut SECONDS: u32 = 0;
|
||||
/// Processes potential timer events. Must be polled regularly
|
||||
pub fn poll() {
|
||||
unsafe {
|
||||
if read_reg::<u32>(0xf000_3818) == 0 {
|
||||
if read_reg::<u32>(BASE + 0x18) == 0 {
|
||||
// No event yet, continue
|
||||
return;
|
||||
}
|
||||
|
||||
// Clear TIMER0 event status, and update time
|
||||
write_reg(0xf000_3818, 1u32);
|
||||
write_reg(BASE + 0x18, 1u32);
|
||||
SECONDS += 1;
|
||||
}
|
||||
}
|
||||
@ -37,9 +39,9 @@ pub fn millis() -> u32 {
|
||||
riscv::interrupt::free(|| {
|
||||
unsafe {
|
||||
// Latch timer value
|
||||
write_reg(0xf000_380c, 1u32);
|
||||
write_reg(BASE + 0x0C, 1u32);
|
||||
// Read timer value
|
||||
let val: u32 = read_reg(0xf000_3810);
|
||||
let val: u32 = read_reg(BASE + 0x10);
|
||||
let val = 60_000_000 - val;
|
||||
(SECONDS * 1000) + val / 60_000
|
||||
}
|
||||
@ -51,9 +53,9 @@ pub fn micros() -> u64 {
|
||||
riscv::interrupt::free(|| {
|
||||
unsafe {
|
||||
// Latch timer value
|
||||
write_reg(0xf000_380c, 1u32);
|
||||
write_reg(BASE + 0x0C, 1u32);
|
||||
// Read timer value
|
||||
let val: u32 = read_reg(0xf000_3810);
|
||||
let val: u32 = read_reg(BASE + 0x10);
|
||||
let val = 60_000_000 - val;
|
||||
(SECONDS as u64 * 1_000_000) + (val as u64 / 60)
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user