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gw: get LiteEth working!

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Link comes up! Not working fully, but that could be firmware too
This commit is contained in:
David Lenfesty 2023-04-15 18:11:16 -06:00
parent 1204be4fa0
commit 3b2af908c7
4 changed files with 36 additions and 23 deletions
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12
gateware/eth.py
View File

@ -42,8 +42,12 @@ class LiteEth(Elaboratable, Interface):
i_rgmii_eth_clocks_rx=self.eth_interface.rx_clk, i_rgmii_eth_clocks_rx=self.eth_interface.rx_clk,
o_rgmii_eth_rst_n=self.eth_interface.rst, o_rgmii_eth_rst_n=self.eth_interface.rst,
i_rgmii_eth_int_n=Const(1), i_rgmii_eth_int_n=Const(1),
# TODO actually fix the platform to support this problem.
#i_rgmii_eth_mdio=self.eth_interface.mdio, # Bad hacks
o_rgmii_eth_mdio_o=self.eth_interface.mdio.o,
o_rgmii_eth_mdio_oe=self.eth_interface.mdio.oe,
i_rgmii_eth_mdio_i=self.eth_interface.mdio.i,
o_rgmii_eth_mdc=self.eth_interface.mdc, o_rgmii_eth_mdc=self.eth_interface.mdc,
i_rgmii_eth_rx_ctl=self.eth_interface.rx_ctl, i_rgmii_eth_rx_ctl=self.eth_interface.rx_ctl,
i_rgmii_eth_rx_data=self.eth_interface.rx_data, i_rgmii_eth_rx_data=self.eth_interface.rx_data,
@ -66,8 +70,6 @@ class LiteEth(Elaboratable, Interface):
o_interrupt=self.interrupt, o_interrupt=self.interrupt,
) )
# TODO connect ethernet interface
m.submodules.core = core m.submodules.core = core
return m return m
@ -81,7 +83,7 @@ rgmii_layout = [
# TODO is this not IO? why does LiteEth say input? # TODO is this not IO? why does LiteEth say input?
# I think the answer is it uses a primitive, not 100% right now # I think the answer is it uses a primitive, not 100% right now
("mdio", pin_layout(1, "i")), ("mdio", pin_layout(1, "io")),
("mdc", pin_layout(1, "o")), ("mdc", pin_layout(1, "o")),
("rx_ctl", pin_layout(1, "i")), ("rx_ctl", pin_layout(1, "i")),
("rx_data", pin_layout(4, "i")), ("rx_data", pin_layout(4, "i")),

23
gateware/liteeth/gateware/liteeth_core.v
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@ -24,7 +24,9 @@ module liteeth_core (
input wire rgmii_eth_clocks_rx, input wire rgmii_eth_clocks_rx,
output wire rgmii_eth_rst_n, output wire rgmii_eth_rst_n,
input wire rgmii_eth_int_n, input wire rgmii_eth_int_n,
input wire rgmii_eth_mdio, output wire rgmii_eth_mdio_o,
output wire rgmii_eth_mdio_oe,
input wire rgmii_eth_mdio_i,
output wire rgmii_eth_mdc, output wire rgmii_eth_mdc,
input wire rgmii_eth_rx_ctl, input wire rgmii_eth_rx_ctl,
input wire [3:0] rgmii_eth_rx_data, input wire [3:0] rgmii_eth_rx_data,
@ -3882,14 +3884,17 @@ IDDRX1F IDDRX1F_4(
.Q1(main_maccore_ethphy_rx_data[7]) .Q1(main_maccore_ethphy_rx_data[7])
); );
TRELLIS_IO #( //TRELLIS_IO #(
.DIR("BIDIR") // .DIR("BIDIR")
) TRELLIS_IO ( //) TRELLIS_IO (
.B(rgmii_eth_mdio), // .B(rgmii_eth_mdio),
.I(main_maccore_ethphy_data_w), // .I(main_maccore_ethphy_data_w),
.T((~main_maccore_ethphy_data_oe)), // .T((~main_maccore_ethphy_data_oe)),
.O(main_maccore_ethphy_data_r) // .O(main_maccore_ethphy_data_r)
); //);
assign main_maccore_ethphy_data_r = rgmii_eth_mdio_i;
assign rgmii_eth_mdio_o = main_maccore_ethphy_data_w;
assign rgmii_eth_mdio_oe = main_maccore_ethphy_data_oe;
endmodule endmodule

14
gateware/main.py
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@ -19,6 +19,7 @@ import os
from memory import * from memory import *
from led import * from led import *
from timer import *
from eth import * from eth import *
import i2c import i2c
@ -122,7 +123,7 @@ class Core(Elaboratable):
fw = load_firmware_for_mem() fw = load_firmware_for_mem()
# Hook up memory space # Hook up memory space
self.rom = ROM(size_bytes=12288, data=fw) self.rom = ROM(size_bytes=1024 * 64, data=fw)
m.submodules.rom = self.rom m.submodules.rom = self.rom
# Problem: not sure to handle how we do byte vs word addressing properly # Problem: not sure to handle how we do byte vs word addressing properly
# So doing this shift is a bit of a hacky way to impl anything # So doing this shift is a bit of a hacky way to impl anything
@ -131,14 +132,19 @@ class Core(Elaboratable):
self.ram = RAM() self.ram = RAM()
m.submodules.ram = self.ram m.submodules.ram = self.ram
start, _stop, _step = self.decoder.add(self.ram) start, _stop, _step = self.decoder.add(self.ram, addr=0x01100000)
print(f"RAM added at 0x{start:08x}") print(f"RAM added at 0x{start:08x}")
self.led = LEDPeripheral(self.led_signal) self.led = LEDPeripheral(self.led_signal)
m.submodules.led = self.led m.submodules.led = self.led
start, _stop, _step = self.decoder.add(self.led) start, _stop, _step = self.decoder.add(self.led, addr=0x01200000)
print(f"LED added at 0x{start:08x}") print(f"LED added at 0x{start:08x}")
self.timer = TimerPeripheral(50e6, 1e3)
m.submodules.timer = self.timer
start, _stop, _step = self.decoder.add(self.timer, addr=0x01300000)
print(f"Timer added at 0x{start:08x}")
# TODO how to set addr_width? # TODO how to set addr_width?
# Create CSR bus and connect it to Wishbone # Create CSR bus and connect it to Wishbone
self.csr = csr.Decoder(addr_width=10, data_width=8) self.csr = csr.Decoder(addr_width=10, data_width=8)
@ -240,7 +246,7 @@ if __name__ == "__main__":
if args.build: if args.build:
# Overrides are available via AMARANTH_<override_variable_name> env variable, or kwarg # Overrides are available via AMARANTH_<override_variable_name> env variable, or kwarg
# TODO fix platform so I don't have to manually specify MDIO signal # TODO fix platform so I don't have to manually specify MDIO signal
Colorlight_i9_Platform().build(SoC(), debug_verilog=args.gen_debug_verilog, nextpnr_opts="--router router1", add_preferences="LOCATE COMP \"top.eth.core.rgmii_eth_mdio\" SITE \"P5\";\n") Colorlight_i9_Platform().build(SoC(), debug_verilog=args.gen_debug_verilog, nextpnr_opts="--router router2")
if args.test: if args.test:
if args.save_vcd: if args.save_vcd:

10
gateware/platforms/colorlight_i9.py
View File

@ -61,10 +61,10 @@ class Colorlight_i9_Platform(LatticeECP5Platform):
# Broadcom B50612D Gigabit Ethernet Transceiver # Broadcom B50612D Gigabit Ethernet Transceiver
Resource("eth_rgmii", 0, Resource("eth_rgmii", 0,
Subsignal("rst", PinsN("P4", dir="o")), Subsignal("rst", Pins("P4", dir="o")),
Subsignal("mdc", Pins("N5", dir="o")), Subsignal("mdc", Pins("N5", dir="o")),
#Subsignal("mdio", Pins("P5", dir="io")), Subsignal("mdio", Pins("P5", dir="io")),
Subsignal("tx_clk", Pins("U19", dir="o")), Subsignal("tx_clk", Pins("U19", dir="i")),
Subsignal("tx_ctl", Pins("P19", dir="o")), Subsignal("tx_ctl", Pins("P19", dir="o")),
Subsignal("tx_data", Pins("U20 T19 T20 R20", dir="o")), Subsignal("tx_data", Pins("U20 T19 T20 R20", dir="o")),
Subsignal("rx_clk", Pins("L19", dir="i")), Subsignal("rx_clk", Pins("L19", dir="i")),
@ -75,9 +75,9 @@ class Colorlight_i9_Platform(LatticeECP5Platform):
# Broadcom B50612D Gigabit Ethernet Transceiver # Broadcom B50612D Gigabit Ethernet Transceiver
Resource("eth_rgmii", 1, Resource("eth_rgmii", 1,
Subsignal("rst", PinsN("P4", dir="o")), Subsignal("rst", Pins("P4", dir="o")),
Subsignal("mdc", Pins("N5", dir="o")), Subsignal("mdc", Pins("N5", dir="o")),
#Subsignal("mdio", Pins("P5", dir="io")), Subsignal("mdio", Pins("P5", dir="io")),
Subsignal("tx_clk", Pins("G1", dir="o")), Subsignal("tx_clk", Pins("G1", dir="o")),
Subsignal("tx_ctl", Pins("K1", dir="o")), Subsignal("tx_ctl", Pins("K1", dir="o")),
Subsignal("tx_data", Pins("G2 H1 J1 J3", dir="o")), Subsignal("tx_data", Pins("G2 H1 J1 J3", dir="o")),