gw: get LiteEth working!
Link comes up! Not working fully, but that could be firmware too
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@ -42,8 +42,12 @@ class LiteEth(Elaboratable, Interface):
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i_rgmii_eth_clocks_rx=self.eth_interface.rx_clk,
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o_rgmii_eth_rst_n=self.eth_interface.rst,
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i_rgmii_eth_int_n=Const(1),
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# TODO actually fix the platform to support this problem.
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#i_rgmii_eth_mdio=self.eth_interface.mdio,
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# Bad hacks
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o_rgmii_eth_mdio_o=self.eth_interface.mdio.o,
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o_rgmii_eth_mdio_oe=self.eth_interface.mdio.oe,
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i_rgmii_eth_mdio_i=self.eth_interface.mdio.i,
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o_rgmii_eth_mdc=self.eth_interface.mdc,
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i_rgmii_eth_rx_ctl=self.eth_interface.rx_ctl,
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i_rgmii_eth_rx_data=self.eth_interface.rx_data,
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@ -66,8 +70,6 @@ class LiteEth(Elaboratable, Interface):
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o_interrupt=self.interrupt,
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)
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# TODO connect ethernet interface
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m.submodules.core = core
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return m
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@ -81,7 +83,7 @@ rgmii_layout = [
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# TODO is this not IO? why does LiteEth say input?
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# I think the answer is it uses a primitive, not 100% right now
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("mdio", pin_layout(1, "i")),
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("mdio", pin_layout(1, "io")),
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("mdc", pin_layout(1, "o")),
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("rx_ctl", pin_layout(1, "i")),
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("rx_data", pin_layout(4, "i")),
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@ -24,7 +24,9 @@ module liteeth_core (
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input wire rgmii_eth_clocks_rx,
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output wire rgmii_eth_rst_n,
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input wire rgmii_eth_int_n,
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input wire rgmii_eth_mdio,
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output wire rgmii_eth_mdio_o,
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output wire rgmii_eth_mdio_oe,
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input wire rgmii_eth_mdio_i,
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output wire rgmii_eth_mdc,
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input wire rgmii_eth_rx_ctl,
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input wire [3:0] rgmii_eth_rx_data,
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@ -3882,14 +3884,17 @@ IDDRX1F IDDRX1F_4(
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.Q1(main_maccore_ethphy_rx_data[7])
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);
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TRELLIS_IO #(
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.DIR("BIDIR")
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) TRELLIS_IO (
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.B(rgmii_eth_mdio),
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.I(main_maccore_ethphy_data_w),
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.T((~main_maccore_ethphy_data_oe)),
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.O(main_maccore_ethphy_data_r)
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);
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//TRELLIS_IO #(
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// .DIR("BIDIR")
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//) TRELLIS_IO (
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// .B(rgmii_eth_mdio),
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// .I(main_maccore_ethphy_data_w),
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// .T((~main_maccore_ethphy_data_oe)),
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// .O(main_maccore_ethphy_data_r)
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//);
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assign main_maccore_ethphy_data_r = rgmii_eth_mdio_i;
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assign rgmii_eth_mdio_o = main_maccore_ethphy_data_w;
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assign rgmii_eth_mdio_oe = main_maccore_ethphy_data_oe;
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endmodule
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@ -19,6 +19,7 @@ import os
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from memory import *
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from led import *
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from timer import *
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from eth import *
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import i2c
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@ -122,7 +123,7 @@ class Core(Elaboratable):
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fw = load_firmware_for_mem()
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# Hook up memory space
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self.rom = ROM(size_bytes=12288, data=fw)
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self.rom = ROM(size_bytes=1024 * 64, data=fw)
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m.submodules.rom = self.rom
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# Problem: not sure to handle how we do byte vs word addressing properly
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# So doing this shift is a bit of a hacky way to impl anything
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@ -131,14 +132,19 @@ class Core(Elaboratable):
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self.ram = RAM()
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m.submodules.ram = self.ram
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start, _stop, _step = self.decoder.add(self.ram)
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start, _stop, _step = self.decoder.add(self.ram, addr=0x01100000)
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print(f"RAM added at 0x{start:08x}")
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self.led = LEDPeripheral(self.led_signal)
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m.submodules.led = self.led
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start, _stop, _step = self.decoder.add(self.led)
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start, _stop, _step = self.decoder.add(self.led, addr=0x01200000)
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print(f"LED added at 0x{start:08x}")
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self.timer = TimerPeripheral(50e6, 1e3)
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m.submodules.timer = self.timer
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start, _stop, _step = self.decoder.add(self.timer, addr=0x01300000)
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print(f"Timer added at 0x{start:08x}")
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# TODO how to set addr_width?
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# Create CSR bus and connect it to Wishbone
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self.csr = csr.Decoder(addr_width=10, data_width=8)
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@ -240,7 +246,7 @@ if __name__ == "__main__":
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if args.build:
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# Overrides are available via AMARANTH_<override_variable_name> env variable, or kwarg
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# TODO fix platform so I don't have to manually specify MDIO signal
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Colorlight_i9_Platform().build(SoC(), debug_verilog=args.gen_debug_verilog, nextpnr_opts="--router router1", add_preferences="LOCATE COMP \"top.eth.core.rgmii_eth_mdio\" SITE \"P5\";\n")
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Colorlight_i9_Platform().build(SoC(), debug_verilog=args.gen_debug_verilog, nextpnr_opts="--router router2")
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if args.test:
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if args.save_vcd:
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@ -61,10 +61,10 @@ class Colorlight_i9_Platform(LatticeECP5Platform):
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# Broadcom B50612D Gigabit Ethernet Transceiver
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Resource("eth_rgmii", 0,
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Subsignal("rst", PinsN("P4", dir="o")),
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Subsignal("rst", Pins("P4", dir="o")),
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Subsignal("mdc", Pins("N5", dir="o")),
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#Subsignal("mdio", Pins("P5", dir="io")),
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Subsignal("tx_clk", Pins("U19", dir="o")),
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Subsignal("mdio", Pins("P5", dir="io")),
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Subsignal("tx_clk", Pins("U19", dir="i")),
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Subsignal("tx_ctl", Pins("P19", dir="o")),
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Subsignal("tx_data", Pins("U20 T19 T20 R20", dir="o")),
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Subsignal("rx_clk", Pins("L19", dir="i")),
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@ -75,9 +75,9 @@ class Colorlight_i9_Platform(LatticeECP5Platform):
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# Broadcom B50612D Gigabit Ethernet Transceiver
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Resource("eth_rgmii", 1,
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Subsignal("rst", PinsN("P4", dir="o")),
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Subsignal("rst", Pins("P4", dir="o")),
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Subsignal("mdc", Pins("N5", dir="o")),
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#Subsignal("mdio", Pins("P5", dir="io")),
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Subsignal("mdio", Pins("P5", dir="io")),
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Subsignal("tx_clk", Pins("G1", dir="o")),
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Subsignal("tx_ctl", Pins("K1", dir="o")),
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Subsignal("tx_data", Pins("G2 H1 J1 J3", dir="o")),
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