diff --git a/gateware/eth.py b/gateware/eth.py
new file mode 100644
index 0000000..787e707
--- /dev/null
+++ b/gateware/eth.py
@@ -0,0 +1,27 @@
+from amaranth import *
+from amaranth_soc.wishbone.bus import Interface
+
+# TODO maybe this should just call liteeth_gen to close the loop?
+class LiteEth(Elaboratable, Interface):
+    def __init__(self):
+
+        # TODO change ADDR width
+        Interface.__init__(self, addr_width=32, data_width=32)
+
+        self.rgmii_eth_clocks_tx = Signal()
+
+
+    def elaborate(self, platform):
+        platform.add_file("liteeth_core.v", open("liteeth/gateware/liteeth_core.v", 'r').read())
+
+        m = Module()
+
+        core = Instance(
+            "liteeth_core",
+            i_sys_clock=ClockSignal(),
+            o_rgmii_eth_clocks_tx=self.rgmii_eth_clocks_tx,
+        )
+
+        m.submodules.core = core
+
+        return m
\ No newline at end of file
diff --git a/gateware/gen_liteeth.sh b/gateware/gen_liteeth.sh
new file mode 100644
index 0000000..e6104cf
--- /dev/null
+++ b/gateware/gen_liteeth.sh
@@ -0,0 +1,3 @@
+#!/usr/bin/env sh
+
+liteeth_gen --output-dir liteeth  liteeth_config.yaml
\ No newline at end of file
diff --git a/gateware/liteeth_config.yaml b/gateware/liteeth_config.yaml
new file mode 100644
index 0000000..84c6fc3
--- /dev/null
+++ b/gateware/liteeth_config.yaml
@@ -0,0 +1,9 @@
+clk_freq: 10e6
+phy: LiteEthECP5PHYRGMII
+core: wishbone
+endianness: little
+
+# THese shouldn't be needed
+device: LFE5U-45F-6BG381C
+vendor: lattice
+toolchain: trellis