gateware: start spreading out into a couple modules
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296206524c
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5619482029
34
gateware/led.py
Normal file
34
gateware/led.py
Normal file
@ -0,0 +1,34 @@
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from amaranth import *
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from amaranth_soc.wishbone import *
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class LEDPeripheral(Elaboratable, Interface):
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def __init__(self, led_signal):
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Interface.__init__(self, addr_width=1, data_width=32)
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memory_map = MemoryMap(addr_width=1, data_width=32)
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#memory_map.add_resource("my_led", name="led_peripheral", size=1)
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self.memory_map = memory_map
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self.led = led_signal
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def elaborate(self, platform):
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m = Module()
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storage = Signal(1)
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# Always update read values (both wishbone and the LED outpu)
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m.d.comb += [
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self.dat_r[0].eq(storage),
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self.led.eq(storage),
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]
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m.d.sync += self.ack.eq(0) # default to no ack
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with m.If(self.cyc & self.stb):
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# single cycle ack when CYC and STB are asserted
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m.d.sync += self.ack.eq(1)
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# Write to our storage register if the value has changed
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with m.If(self.we):
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m.d.sync += storage.eq(self.dat_w[0])
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return m
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173
gateware/main.py
173
gateware/main.py
@ -3,160 +3,17 @@
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from amaranth import *
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from amaranth.sim import *
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from amaranth_boards import colorlight_i9
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from amaranth_soc.wishbone import Interface, Arbiter, Decoder
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from amaranth_soc.memory import MemoryMap
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from amaranth_soc.wishbone import *
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from minerva.core import Minerva
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from typing import List
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from argparse import ArgumentParser
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class Blinky(Elaboratable):
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def __init__(self):
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self.count = Signal(64)
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def elaborate(self, platform):
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led = platform.request("led")
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m = Module()
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# Counter
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m.d.sync += self.count.eq(self.count + 1)
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with m.If(self.count >= 50000000):
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m.d.sync += self.count.eq(0)
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m.d.sync += led.eq(~led)
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return m
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# To change clock domain of a module:
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# new_thing = DomainRenamer("new_clock")(MyElaboratable())
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# We sub-class wishbone.Interface here because it needs to be a bus object to be added as a window to Wishbone stuff
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class ROM(Elaboratable, Interface):
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def __init__(self, data=None):
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#self.size = len(data)
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self.data = Memory(width=32, depth=(4096 >> 2), init=data)
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self.r = self.data.read_port()
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# Need to init Interface
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Interface.__init__(self, addr_width=10, data_width=32)
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# This is effectively a "window", and it has a certain set of resources
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# 12 = log2(4096)
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memory_map = MemoryMap(addr_width=10, data_width=32)
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# TODO need to unify how I deal with size
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# In this case, one resource, which is out memory
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memory_map.add_resource(self.data, name="rom_data", size=(4096 >> 2))
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self.memory_map = memory_map
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# Connects memory port signals to wishbone interface
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def elaborate(self, platform):
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# Stolen from https://vivonomicon.com/2020/04/14/learning-fpga-design-with-nmigen/
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m = Module()
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# Register the read port submodule.
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m.submodules.r = self.r
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# 'ack' signal should rest at 0.
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m.d.sync += self.ack.eq( 0 )
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# Simulated reads only take one cycle, but only acknowledge
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# them after 'cyc' and 'stb' are asserted.
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with m.If( self.cyc ):
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m.d.sync += self.ack.eq( self.stb )
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# Set 'dat_r' bus signal to the value in the
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# requested 'data' array index.
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m.d.comb += [
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self.r.addr.eq( self.adr ),
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self.dat_r.eq( self.r.data )
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]
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# End of simulated memory module.
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return m
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# TODO support read segmentation or whatever it's called, where you read/write certian bytes from memory
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# Otherwise we can't store individual bytes, and this will wreck shit in weird ways.
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class RAM(Elaboratable, Interface):
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def __init__(self):
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#self.size = len(data)
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self.data = Memory(width=32, depth=(4096 >> 2))
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self.r = self.data.read_port()
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self.w = self.data.write_port()
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# Need to init Interface
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Interface.__init__(self, addr_width=10, data_width=32)
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# This is effectively a "window", and it has a certain set of resources
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# 12 = log2(4096)
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memory_map = MemoryMap(addr_width=10, data_width=32)
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# TODO need to unify how I deal with size
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# In this case, one resource, which is out memory
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memory_map.add_resource(self.data, name="ram_data", size=(4096 >> 2))
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self.memory_map = memory_map
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# Connects memory port signals to wishbone interface
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def elaborate(self, platform):
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# Stolen from https://vivonomicon.com/2020/04/14/learning-fpga-design-with-nmigen/
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m = Module()
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# Register the read port submodule.
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m.submodules.r = self.r
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m.submodules.w = self.w
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# 'ack' signal should rest at 0.
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m.d.sync += self.ack.eq(0)
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# Simulated reads only take one cycle, but only acknowledge
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# them after 'cyc' and 'stb' are asserted.
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with m.If( self.cyc & self.stb):
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m.d.sync += self.ack.eq(1)
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# Write to address if we are writing
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with m.If(self.we):
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m.d.sync += self.w.en.eq(1)
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# Set 'dat_r' bus signal to the value in the
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# requested 'data' array index.
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m.d.comb += [
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self.r.addr.eq( self.adr ),
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self.dat_r.eq( self.r.data ),
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self.w.addr.eq(self.adr),
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self.w.data.eq(self.dat_w),
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]
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# End of simulated memory module.
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return m
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class LEDPeripheral(Elaboratable, Interface):
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def __init__(self, led_signal):
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Interface.__init__(self, addr_width=1, data_width=32)
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memory_map = MemoryMap(addr_width=1, data_width=32)
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#memory_map.add_resource("my_led", name="led_peripheral", size=1)
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self.memory_map = memory_map
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self.led = led_signal
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def elaborate(self, platform):
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m = Module()
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storage = Signal(1)
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# Always update read values (both wishbone and the LED outpu)
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m.d.comb += [
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self.dat_r[0].eq(storage),
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self.led.eq(storage),
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]
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m.d.sync += self.ack.eq(0) # default to no ack
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with m.If(self.cyc & self.stb):
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# single cycle ack when CYC and STB are asserted
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m.d.sync += self.ack.eq(1)
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# Write to our storage register if the value has changed
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with m.If(self.we):
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m.d.sync += storage.eq(self.dat_w[0])
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return m
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# TODO clean this up, generate binary here, maybe even run cargo build
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def load_firmware_for_mem() -> List[int]:
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@ -247,32 +104,18 @@ class SoC(Elaboratable):
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pass
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def elaborate(self, platform):
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m = Module()
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if platform is not None:
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led_signal = platform.request("led")
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else:
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# platform is None in simulation, so provide harnesses for required signals
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led_signal = Signal()
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led_signal = platform.request("led")
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core = Core(led_signal)
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m.submodules.core = core
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return Core(led_signal)
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return m
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# TODO add more harnessing
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class TestDevice(Elaboratable):
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def __init__(self):
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pass
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def elaborate(self, platform):
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m = Module()
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led_signal = Signal()
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core = Core(led_signal)
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m.submodules.core = core
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return m
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# TODO add structure to add regression tests
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def run_sim():
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dut = TestDevice()
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dut = SoC()
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sim = Simulator(dut)
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def proc():
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100
gateware/memory.py
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100
gateware/memory.py
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@ -0,0 +1,100 @@
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from amaranth import *
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from amaranth_soc.wishbone import *
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from amaranth_soc.memory import *
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# We sub-class wishbone.Interface here because it needs to be a bus object to be added as a window to Wishbone stuff
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class ROM(Elaboratable, Interface):
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def __init__(self, data=None):
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#self.size = len(data)
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self.data = Memory(width=32, depth=(4096 >> 2), init=data)
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self.r = self.data.read_port()
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# Need to init Interface
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Interface.__init__(self, addr_width=10, data_width=32)
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# This is effectively a "window", and it has a certain set of resources
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# 12 = log2(4096)
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memory_map = MemoryMap(addr_width=10, data_width=32)
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# TODO need to unify how I deal with size
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# In this case, one resource, which is out memory
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memory_map.add_resource(self.data, name="rom_data", size=(4096 >> 2))
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self.memory_map = memory_map
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# Connects memory port signals to wishbone interface
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def elaborate(self, platform):
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# Stolen from https://vivonomicon.com/2020/04/14/learning-fpga-design-with-nmigen/
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m = Module()
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# Register the read port submodule.
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m.submodules.r = self.r
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# 'ack' signal should rest at 0.
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m.d.sync += self.ack.eq( 0 )
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# Simulated reads only take one cycle, but only acknowledge
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# them after 'cyc' and 'stb' are asserted.
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with m.If( self.cyc ):
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m.d.sync += self.ack.eq( self.stb )
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# Set 'dat_r' bus signal to the value in the
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# requested 'data' array index.
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m.d.comb += [
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self.r.addr.eq( self.adr ),
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self.dat_r.eq( self.r.data )
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]
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# End of simulated memory module.
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return m
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# TODO support read segmentation or whatever it's called, where you read/write certian bytes from memory
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# Otherwise we can't store individual bytes, and this will wreck shit in weird ways.
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class RAM(Elaboratable, Interface):
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def __init__(self):
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#self.size = len(data)
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self.data = Memory(width=32, depth=(4096 >> 2))
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self.r = self.data.read_port()
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self.w = self.data.write_port()
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# Need to init Interface
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Interface.__init__(self, addr_width=10, data_width=32)
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# This is effectively a "window", and it has a certain set of resources
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# 12 = log2(4096)
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memory_map = MemoryMap(addr_width=10, data_width=32)
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# TODO need to unify how I deal with size
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# In this case, one resource, which is out memory
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memory_map.add_resource(self.data, name="ram_data", size=(4096 >> 2))
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self.memory_map = memory_map
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# Connects memory port signals to wishbone interface
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def elaborate(self, platform):
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# Stolen from https://vivonomicon.com/2020/04/14/learning-fpga-design-with-nmigen/
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m = Module()
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# Register the read port submodule.
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m.submodules.r = self.r
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m.submodules.w = self.w
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# 'ack' signal should rest at 0.
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m.d.sync += self.ack.eq(0)
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# Simulated reads only take one cycle, but only acknowledge
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# them after 'cyc' and 'stb' are asserted.
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with m.If( self.cyc & self.stb):
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m.d.sync += self.ack.eq(1)
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# Write to address if we are writing
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with m.If(self.we):
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m.d.sync += self.w.en.eq(1)
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# Set 'dat_r' bus signal to the value in the
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# requested 'data' array index.
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m.d.comb += [
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self.r.addr.eq( self.adr ),
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self.dat_r.eq( self.r.data ),
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self.w.addr.eq(self.adr),
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self.w.data.eq(self.dat_w),
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]
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# End of simulated memory module.
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return m
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