gateware: add PLL and generate two clocks

TODO is make a proper clock gen object, maybe it could run ecppll by
itself?

gateware/main.py

@@ -39,12 +39,14 @@ def load_firmware_for_mem() -> List[int]:
         return out
 
 class Core(Elaboratable):
-    def __init__(self, led_signal):
+    def __init__(self, clk25, led_signal, eth_interface):
         self.count = Signal(64)
         self.cpu = Minerva(reset_address=0x01000000)
         self.arbiter = Arbiter(addr_width=32, data_width=32)
-        self.decoder = Decoder(addr_width=32, data_width=32)
+        self.decoder = Decoder(addr_width=32, data_width=32, features=["err"])
+        self.clk25 = clk25
         self.led_signal = led_signal
+        self.eth_interface = eth_interface
 
     def elaborate(self, platform):
         m = Module()
@@ -52,6 +54,29 @@ class Core(Elaboratable):
         m.submodules.arbiter = self.arbiter
         m.submodules.decoder = self.decoder
 
+        # Create main and sampling clock, using PLL and 25MHz input clock
+        platform.add_file("pll.v", open("pll.v", "r").read())
+        sys_clk = Signal()
+        sample_clk = Signal()
+        pll = Instance(
+            "pll",
+            i_clkin=self.clk25,
+            o_clkout0=sys_clk,
+            o_clkout1=sample_clk,
+        )
+        m.submodules.pll = pll
+
+        # Create new clock domains
+        m.domains += ClockDomain("sync")
+        m.domains += ClockDomain("sample")
+        m.d.comb += ClockSignal("sync").eq(sys_clk)
+        m.d.comb += ClockSignal("sample").eq(sample_clk)
+
+        # Add clock constraints
+        if platform is not None:
+            platform.add_clock_constraint(sys_clk, 50e6)
+            platform.add_clock_constraint(sample_clk, 10e6)
+
         # Connect ibus and dbus together for simplicity for now
         minerva_wb_features = ["cti", "bte", "err"]
         self.ibus = Interface(addr_width=32, data_width=32, features=minerva_wb_features)