fw: start janky ethernet bringup testing

firmware/src/eth.rs

@@ -0,0 +1,41 @@
+//! Quick and hacky ethernet thing to test
+
+const LITEETH_BASE: u32 = 0x0050_0000;
+
+
+const ETHMAC_SRAM_WRITER_EV_PENDING: u32 = LITEETH_BASE + 0x810;
+const ETHMAC_SRAM_WRITER_EV_ENABLE: u32 = LITEETH_BASE + 0x814;
+const ETHMAC_SRAM_READER_EV_PENDING: u32 = LITEETH_BASE + 0x830;
+const ETHMAC_SRAM_READER_EV_ENABLE: u32 = LITEETH_BASE + 0x834;
+
+fn write_u32_reg(addr: u32, value: u32) {
+    unsafe { *(addr as *mut u32) = value; }
+}
+
+fn read_u32_reg(addr: u32) -> u32 {
+    unsafe {
+        return *(addr as *mut u32);
+    }
+}
+
+pub fn is_wishbone_correct() -> bool {
+    let value = read_u32_reg(LITEETH_BASE + 4);
+
+    // If this isn't true, we screwed.
+    return value == 0x12345678;
+}
+
+pub fn init() {
+    // Clear any potential pending events
+    write_u32_reg(ETHMAC_SRAM_WRITER_EV_PENDING, 1);
+    write_u32_reg(ETHMAC_SRAM_READER_EV_PENDING, 1);
+
+    // Disable all events
+    write_u32_reg(ETHMAC_SRAM_WRITER_EV_ENABLE, 0);
+    write_u32_reg(ETHMAC_SRAM_READER_EV_ENABLE, 0);
+}
+
+pub fn tranmsit() {
+
+}
+

firmware/src/main.rs

@@ -7,17 +7,28 @@ use core::{arch::asm, ptr::write};
 
 use riscv_rt::entry;
 
+mod eth;
+
 // use `main` as the entry point of this application
 // `main` is not allowed to return
 #[entry]
 fn main() -> ! {
+    //eth::init();
+
+    let blink_period = if eth::is_wishbone_correct() {
+        10_000_000
+    } else {
+        500_000
+    };
+
+
     // do something here
     loop {
         unsafe {
             write(0x01002000 as *mut u32, 0);
-            busy_wait(10_000_000);
+            busy_wait(blink_period);
             write(0x01002000 as *mut u32, 1);
-            busy_wait(10_000_000);
+            busy_wait(blink_period);
         }
     }
 }