diff --git a/Dockerfile b/Dockerfile
index 26f9e3e..20d8e1e 100644
--- a/Dockerfile
+++ b/Dockerfile
@@ -28,6 +28,11 @@ RUN tar -xzf oss-cad-suite-linux-x64-20230603.tgz
 RUN rm oss-cad-suite-linux-x64-20230603.tgz
 ENV PATH="/oss-cad-suite/bin:${PATH}"
 
+# Apply patch to fix migen
+COPY migen.patch /litex/migen/migen.patch
+RUN cd /litex/migen && git apply /litex/migen/migen.patch
+RUN pip install --editable /litex/migen
+
 # Delete package cache to keep size small
 RUN apt-get clean
 
diff --git a/gateware/litex_main.py b/gateware/litex_main.py
index 42c5d43..6b7a37d 100755
--- a/gateware/litex_main.py
+++ b/gateware/litex_main.py
@@ -143,11 +143,11 @@ class BaseSoC(SoCCore):
             if with_video_framebuffer:
                 self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
 
-        #samplers = [Sampler(platform.request("adc", i)) for i in range(3)]
-        #self.submodules.sampler_controller = SamplerController(samplers, buffer_len=2048 * 10)
-        ### TODO better way to do this?
-        #sampler_region = SoCRegion(origin=None, size=0x4000, cached=False)
-        #self.bus.add_slave(name="sampler", slave=self.sampler_controller.bus, region=sampler_region)
+        samplers = [Sampler(platform.request("adc", i)) for i in range(3)]
+        self.submodules.sampler_controller = SamplerController(samplers, buffer_len=2048 * 10)
+        # TODO better way to do this?
+        sampler_region = SoCRegion(origin=None, size=0x4000, cached=False)
+        self.bus.add_slave(name="sampler", slave=self.sampler_controller.bus, region=sampler_region)
 
 # Build --------------------------------------------------------------------------------------------
 
diff --git a/migen.patch b/migen.patch
new file mode 100755
index 0000000..52e3689
--- /dev/null
+++ b/migen.patch
@@ -0,0 +1,26 @@
+diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
+index 0865e76..c16db10 100644
+--- a/migen/fhdl/structure.py
++++ b/migen/fhdl/structure.py
+@@ -35,6 +35,8 @@ class _Value(DUID):
+                 return a.value == b.value
+             if isinstance(a, Signal) and isinstance(b, Signal):
+                 return a is b
++            if isinstance(a, ClockSignal) and isinstance(b, ClockSignal):
++                return a.cd == b.cd
+             if (isinstance(a, Constant) and isinstance(b, Signal)
+                     or isinstance(a, Signal) and isinstance(b, Constant)):
+                 return False
+diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
+index 9bde3de..379c52f 100644
+--- a/migen/fhdl/verilog.py
++++ b/migen/fhdl/verilog.py
+@@ -56,6 +56,8 @@ def _printexpr(ns, node):
+         return _printconstant(node)
+     elif isinstance(node, Signal):
+         return ns.get_name(node), node.signed
++    elif isinstance(node, ClockSignal):
++        return ns.get_name(node), False
+     elif isinstance(node, _Operator):
+         arity = len(node.operands)
+         r1, s1 = _printexpr(ns, node.operands[0])