diff --git a/gateware/eth.py b/gateware/eth.py
index 3c65008..7819f43 100644
--- a/gateware/eth.py
+++ b/gateware/eth.py
@@ -1,6 +1,7 @@
 from amaranth import *
 from amaranth.lib.io import pin_layout
 from amaranth_soc.wishbone.bus import Interface
+from amaranth_soc.memory import MemoryMap
 
 
 __all__ = ["LiteEth", "rgmii_layout"]
@@ -8,12 +9,15 @@ __all__ = ["LiteEth", "rgmii_layout"]
 
 # TODO maybe this should just call liteeth_gen to close the loop?
 class LiteEth(Elaboratable, Interface):
-    def __init__(self):
+    def __init__(self, eth_interface):
+        self.eth_interface = eth_interface
 
         # Addr width is 13 bits to accomodate 0x1FFF, which is well p
         Interface.__init__(self, addr_width=13, data_width=32, granularity=8, features=["cti", "bte", "err"])
-
-        self.rgmii_eth_clocks_tx = Signal()
+        # TODO I need to understand the semantics here better
+        memory_map = MemoryMap(addr_width=15, data_width=8)
+        #memory_map.add_resource(self, name="LiteETH", size=0x2000)
+        self.memory_map = memory_map
 
         self.interrupt = Signal()
 
@@ -32,7 +36,16 @@ class LiteEth(Elaboratable, Interface):
             i_sys_clock=ClockSignal(),
 
             # RGMII signals
-            o_rgmii_eth_clocks_tx=self.rgmii_eth_clocks_tx,
+            o_rgmii_eth_clocks_tx=self.eth_interface.tx_clk,
+            i_rgmii_eth_clocks_rx=self.eth_interface.rx_clk,
+            o_rgmii_eth_rst_n=self.eth_interface.rst,
+            i_rgmii_eth_int_n=Const(1),
+            i_rgmii_eth_mdio=self.eth_interface.mdio,
+            o_rgmii_eth_mdc=self.eth_interface.mdc,
+            i_rgmii_eth_rx_ctl=self.eth_interface.rx_ctl,
+            i_rgmii_eth_rx_data=self.eth_interface.rx_data,
+            o_rgmii_eth_tx_ctl=self.eth_interface.tx_ctl,
+            o_rgmii_eth_tx_data=self.eth_interface.tx_data,
 
             # Wishbone all the things
             i_wishbone_adr=self.adr,
@@ -49,15 +62,17 @@ class LiteEth(Elaboratable, Interface):
             o_interrupt=self.interrupt,
         )
 
+        # TODO connect ethernet interface
+
         m.submodules.core = core
 
         return m
 
 
 rgmii_layout = [
-    ("clocks_tx", pin_layout(1, "o")),
-    ("clocks_rx", pin_layout(1, "i")),
-    ("rst_n", pin_layout(1, "o")),
+    ("tx_clk", pin_layout(1, "o")),
+    ("rx_clk", pin_layout(1, "i")),
+    ("rst", pin_layout(1, "o")),
     ("int_n", pin_layout(1, "i")),
 
     # TODO is this not IO? why does LiteEth say input?
diff --git a/gateware/main.py b/gateware/main.py
index 9fbc3a6..cc01a4d 100644
--- a/gateware/main.py
+++ b/gateware/main.py
@@ -124,13 +124,16 @@ class Core(Elaboratable):
         start, _stop, _step = self.decoder.add(self.led)
         print(f"LED added at 0x{start:08x}")
 
-        # Connect arbiter to decoder
-        m.d.comb += self.arbiter.bus.connect(self.decoder.bus)
-
         m.submodules.uart = uart.UART(10e6)
 
         # Ethernet
-        m.submodules.eth = LiteEth()
+        self.eth = LiteEth(self.eth_interface)
+        m.submodules.eth = self.eth
+        start, _stop, _step = self.decoder.add(self.eth)
+        print(f"LiteETH added at 0x{start:08x}")
+
+        # Connect arbiter to decoder
+        m.d.comb += self.arbiter.bus.connect(self.decoder.bus)
 
         # Counter
         #m.d.sync += self.count.eq(self.count + 1)
@@ -146,12 +149,16 @@ class SoC(Elaboratable):
 
     def elaborate(self, platform):
         if platform is not None:
+            clk25 = platform.request("clk25")
             led_signal = platform.request("led")
+            ethernet_interface = platform.request("eth_rgmii", 1)
         else:
             # platform is None in simulation, so provide harnesses for required signals
+            clk25 = Signal() # TODO unsure if this will work in sim
             led_signal = Signal()
+            ethernet_interface = Record(rgmii_layout)
 
-        return Core(led_signal)
+        return Core(clk25, led_signal, ethernet_interface)
 
 
 # TODO add structure to add regression tests