From 7e3239700d5c43b881273f5123e5a3a0ae333678 Mon Sep 17 00:00:00 2001 From: David Lenfesty Date: Sat, 17 Jun 2023 15:56:11 +0000 Subject: [PATCH] start playing around with sampler (not working at all, wb issues I think) --- firmware/build_and_strip.sh | 3 ++- firmware/src/main.rs | 41 +++++++++++++++++++++++++++++----- firmware/src/proto.rs | 2 ++ gateware/litex_main.py | 2 +- gateware/platforms/sonar.py | 7 +++++- gateware/sampler/controller.py | 8 +++---- pysonar/__init__.py | 1 + pysonar/command_packets.py | 1 + 8 files changed, 53 insertions(+), 12 deletions(-) diff --git a/firmware/build_and_strip.sh b/firmware/build_and_strip.sh index 63e0c7a..e633a39 100755 --- a/firmware/build_and_strip.sh +++ b/firmware/build_and_strip.sh @@ -2,7 +2,8 @@ DEFMT_LOG=debug cargo build --release if [ $? -ne 0 ] then - exit $? + # Can't use $? because the check itself also updates the return code + exit 1 fi # Account for different toolchains diff --git a/firmware/src/main.rs b/firmware/src/main.rs index 57f7c93..2be3dda 100644 --- a/firmware/src/main.rs +++ b/firmware/src/main.rs @@ -32,6 +32,7 @@ mod logging; mod mcp4726; mod proto; mod uart; +mod sampler; const MAC: [u8; 6] = [0xA0, 0xBB, 0xCC, 0xDD, 0xEE, 0xF0]; @@ -93,6 +94,18 @@ fn main() -> ! { sock.set_timeout(Some(Duration::from_secs(10))) } + let mut data_tx_storage = [0u8; 256]; + let mut data_rx_storage = [0u8; 24]; + let mut data_tx_buf = SocketBuffer::new(&mut data_tx_storage[..]); + let mut data_rx_buf = SocketBuffer::new(&mut data_rx_storage[..]); + let mut data_socket = socket_set.add(TcpSocket::new(data_tx_buf, data_rx_buf)); + { + let mut sock = socket_set.get_mut::(data_socket); + // TODO these values are obscene, should fix the underlying bug + sock.set_keep_alive(Some(Duration::from_secs(2))); + sock.set_timeout(Some(Duration::from_secs(10))) + } + let mut last_blink: u32 = 0; let mut toggle = false; //defmt::info!("Done setup"); @@ -110,23 +123,41 @@ fn main() -> ! { loop { let now = millis(); + iface.poll(Instant::from_millis(now), &mut device, &mut socket_set); + + // TODO first connection to a socket takes a while to establish, and can time out, why? + cmd.run(socket_set.get_mut(command_socket)); + // TODO the need for the second check screams something is unsound somewhere if now - last_blink > 1000 && now > last_blink { last_blink = now; toggle = !toggle; write_led(if toggle { 1 } else { 0 }); - let val: u32 = unsafe { read_reg(0x8000_2000) }; + let mut sock = socket_set.get_mut::(data_socket); + if !sock.is_open() { + sock.listen(3000); + } + + if toggle { + sampler::clear_buffers(); + sampler::start_sampling(); + + let buf = unsafe {sampler::get_sample_buffer(0) }; + let status = sampler::read_status(); + let raw_reg: u32 = unsafe { read_reg(0x8040_0004) }; + defmt::debug!("Start: len: {}, complete: {}, running: {}, status: {}", buf.len(), status.capture_complete, status.sampling, raw_reg); + } else { + sampler::stop_sampling(); + let buf = unsafe {sampler::get_sample_buffer(0) }; + defmt::debug!("Stopped, len: {}", buf.len()); + } } // TODO I think the timer might actually stop until the event is cleared? this may pose // problems, might explain why moving this above the smoltcp stuff "broke" things handle_timer_event(); - iface.poll(Instant::from_millis(now), &mut device, &mut socket_set); - - // TODO first connection to a socket takes a while to establish, and can time out, why? - cmd.run(socket_set.get_mut(command_socket)); } } diff --git a/firmware/src/proto.rs b/firmware/src/proto.rs index 5732cea..6aaef48 100644 --- a/firmware/src/proto.rs +++ b/firmware/src/proto.rs @@ -53,6 +53,8 @@ pub enum Settings { CenterFreq = 5, /// Sampling enabled, 1 to enable, 0 to disable SamplingEnabled = 6, + /// Number of samples acquired after trigger + TriggerRunLen = 7, } #[derive(Clone, Copy, Debug)] diff --git a/gateware/litex_main.py b/gateware/litex_main.py index 6b7a37d..953d7a3 100755 --- a/gateware/litex_main.py +++ b/gateware/litex_main.py @@ -146,7 +146,7 @@ class BaseSoC(SoCCore): samplers = [Sampler(platform.request("adc", i)) for i in range(3)] self.submodules.sampler_controller = SamplerController(samplers, buffer_len=2048 * 10) # TODO better way to do this? - sampler_region = SoCRegion(origin=None, size=0x4000, cached=False) + sampler_region = SoCRegion(origin=None, size=0x0040_0000, cached=False) self.bus.add_slave(name="sampler", slave=self.sampler_controller.bus, region=sampler_region) # Build -------------------------------------------------------------------------------------------- diff --git a/gateware/platforms/sonar.py b/gateware/platforms/sonar.py index 135011d..c717479 100644 --- a/gateware/platforms/sonar.py +++ b/gateware/platforms/sonar.py @@ -27,11 +27,16 @@ _io_v7_0 = [ # Colorlight i9 documented by @smunaut ("user_led_n", 0, Pins("U16"), IOStandard("LVCMOS33")), # Serial - ("serial", 0, + ("serial", 2, Subsignal("tx", Pins("P16")), Subsignal("rx", Pins("L5")), IOStandard("LVCMOS33") ), + ("serial", 3, + Subsignal("tx", Pins("J18")), + Subsignal("rx", Pins("J16")), + IOStandard("LVCMOS33") + ), # TODO the other serial ports diff --git a/gateware/sampler/controller.py b/gateware/sampler/controller.py index d15b1ec..70d262a 100644 --- a/gateware/sampler/controller.py +++ b/gateware/sampler/controller.py @@ -89,13 +89,13 @@ class SamplerController(Module): control_block_addr_width = ceil(log2(num_channels + 1)) # Bus address width - addr_width = control_block_addr_width + sample_mem_addr_width + addr_width = (num_channels + 1) * sample_mem_addr_width # "Master" bus - self.bus = Interface(data_width=32, addr_width=addr_width) + self.bus = Interface(data_width=32, adr_width=addr_width) # Wishbone bus used for mapping control registers - self.control_regs_bus = Interface(data_width=32, addr_width=sample_mem_addr_width) + self.control_regs_bus = Interface(data_width=32, adr_width=sample_mem_addr_width) slaves = [] slaves.append((lambda adr: adr[sample_mem_addr_width:] == 0, self.control_regs_bus)) @@ -154,7 +154,7 @@ class SamplerController(Module): # Handle length values for each sample buffer for i, buffer in enumerate(self.buffers): - cases.update({0x100 + i: rw_register(buffer.len, write=False)}) + cases.update({(0x100 >> 2) + i: rw_register(buffer.len, write=False)}) # Connect up control registers bus self.sync += [ diff --git a/pysonar/__init__.py b/pysonar/__init__.py index 8bba107..29e6540 100644 --- a/pysonar/__init__.py +++ b/pysonar/__init__.py @@ -16,6 +16,7 @@ settings = { "gain": Settings.Gain, "center_frequency": Settings.CenterFreq, "sampling_enabled": Settings.SamplingEnabled, + "trigger_run_len": Settings.TriggerRunLen, } diff --git a/pysonar/command_packets.py b/pysonar/command_packets.py index d5db2f5..8276c43 100644 --- a/pysonar/command_packets.py +++ b/pysonar/command_packets.py @@ -16,6 +16,7 @@ class Settings(IntEnum): Gain = 4 CenterFreq = 5 SamplingEnabled = 6 + TriggerRunLen = 7 @dataclass