fw: formatting

This commit is contained in:
David Lenfesty 2023-06-16 16:30:49 -06:00
parent db1ff6761d
commit 800c6012f2
5 changed files with 68 additions and 64 deletions

View File

@ -1,7 +1,8 @@
use smoltcp::socket::tcp::{Socket, State}; use smoltcp::socket::tcp::{Socket, State};
use crate::proto::{ use crate::proto::{
serialize_response_error, serialize_response_value, PacketParser, ResponsePacket, Settings, ErrorCodes serialize_response_error, serialize_response_value, ErrorCodes, PacketParser, ResponsePacket,
Settings,
}; };
pub struct CommandInterface { pub struct CommandInterface {
@ -70,7 +71,8 @@ impl CommandInterface {
return (0, ()); return (0, ());
} }
let response = serialize_response_error(packet.setting, ErrorCodes::InvalidSetting); let response =
serialize_response_error(packet.setting, ErrorCodes::InvalidSetting);
&tx_buf[0..8].copy_from_slice(&response); &tx_buf[0..8].copy_from_slice(&response);
return (8, ()); return (8, ());
}); });
@ -79,7 +81,12 @@ impl CommandInterface {
} }
}; };
defmt::debug!("Valid packet: {:?}, is_write: {}, value: {}", packet.setting, packet.is_write, packet.value); defmt::debug!(
"Valid packet: {:?}, is_write: {}, value: {}",
packet.setting,
packet.is_write,
packet.value
);
// TODO validate setting values // TODO validate setting values

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@ -69,7 +69,10 @@ impl LiteEthDevice {
write_reg(csr_addr + ETHMAC_SRAM_WRITER_EV_ENABLE, 0u32); write_reg(csr_addr + ETHMAC_SRAM_WRITER_EV_ENABLE, 0u32);
// Return a new device // Return a new device
Some(Self { csr_addr, ethmac_addr }) Some(Self {
csr_addr,
ethmac_addr,
})
} }
} }
@ -196,13 +199,9 @@ impl smoltcp::phy::RxToken for LiteEthRxToken {
F: FnOnce(&mut [u8]) -> R, F: FnOnce(&mut [u8]) -> R,
{ {
// Read the slot number // Read the slot number
let slot = unsafe { let slot = unsafe { read_reg::<u32>(self.csr_addr + ETHMAC_SRAM_WRITER_SLOT) };
read_reg::<u32>(self.csr_addr + ETHMAC_SRAM_WRITER_SLOT)
};
// Read the available length // Read the available length
let len = unsafe { let len = unsafe { read_reg::<u32>(self.csr_addr + ETHMAC_SRAM_WRITER_LENGTH) };
read_reg::<u32>(self.csr_addr + ETHMAC_SRAM_WRITER_LENGTH)
};
let rx_slot_addr: u32 = self.ethmac_addr + slot * SLOT_LEN; let rx_slot_addr: u32 = self.ethmac_addr + slot * SLOT_LEN;
let rx_slot: &mut [u8] = let rx_slot: &mut [u8] =

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@ -1,4 +1,4 @@
use core::{fmt::Write, any::Any}; use core::{any::Any, fmt::Write};
use defmt; use defmt;
@ -29,7 +29,6 @@ unsafe impl defmt::Logger for DefmtLogger {
UART = Some(LitexUart::new(0xf000_4000)); UART = Some(LitexUart::new(0xf000_4000));
} }
let mut dev = UART.unwrap(); let mut dev = UART.unwrap();
for byte in bytes { for byte in bytes {
while let Err(_) = dev.try_put_char(*byte) {} while let Err(_) = dev.try_put_char(*byte) {}

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@ -1,6 +1,5 @@
#![no_std] #![no_std]
#![no_main] #![no_main]
// TODO remove // TODO remove
#![allow(unused)] #![allow(unused)]
@ -15,24 +14,24 @@ use core::{
use embedded_hal::prelude::{_embedded_hal_blocking_i2c_Read, _embedded_hal_blocking_i2c_Write}; use embedded_hal::prelude::{_embedded_hal_blocking_i2c_Read, _embedded_hal_blocking_i2c_Write};
use mcp4726::Status; use mcp4726::Status;
use riscv_rt::entry; use riscv_rt::entry;
use smoltcp::socket::{Socket, self}; use smoltcp::socket::{self, Socket};
use smoltcp::time::Duration; use smoltcp::time::Duration;
use smoltcp::wire::{IpAddress, Ipv4Address}; use smoltcp::wire::{IpAddress, Ipv4Address};
use smoltcp::{ use smoltcp::{
iface::{SocketSet, SocketStorage}, iface::{SocketSet, SocketStorage},
time::Instant,
wire::HardwareAddress,
socket::tcp::Socket as TcpSocket, socket::tcp::Socket as TcpSocket,
socket::tcp::SocketBuffer, socket::tcp::SocketBuffer,
time::Instant,
wire::HardwareAddress,
}; };
mod command_interface;
mod eth; mod eth;
mod i2c; mod i2c;
mod mcp4726;
mod uart;
mod logging; mod logging;
mod mcp4726;
mod proto; mod proto;
mod command_interface; mod uart;
const MAC: [u8; 6] = [0xA0, 0xBB, 0xCC, 0xDD, 0xEE, 0xF0]; const MAC: [u8; 6] = [0xA0, 0xBB, 0xCC, 0xDD, 0xEE, 0xF0];
@ -94,16 +93,15 @@ fn main() -> ! {
sock.set_timeout(Some(Duration::from_secs(10))) sock.set_timeout(Some(Duration::from_secs(10)))
} }
let mut logger_tx_storage = [0u8; 128]; let mut logger_tx_storage = [0u8; 128];
let mut logger_rx_storage = [0u8; 16]; let mut logger_rx_storage = [0u8; 16];
let mut logger_tx_buf = SocketBuffer::new(&mut logger_tx_storage[..]); let mut logger_tx_buf = SocketBuffer::new(&mut logger_tx_storage[..]);
let mut logger_rx_buf = SocketBuffer::new(&mut logger_rx_storage[..]); let mut logger_rx_buf = SocketBuffer::new(&mut logger_rx_storage[..]);
let mut logger_socket = socket_set.add(TcpSocket::new(logger_tx_buf, logger_rx_buf)); let mut logger_socket = socket_set.add(TcpSocket::new(logger_tx_buf, logger_rx_buf));
unsafe { logging::set_logger_socket(Some(socket_set.get_mut::<TcpSocket>(logger_socket))); } unsafe {
logging::set_logger_socket(Some(socket_set.get_mut::<TcpSocket>(logger_socket)));
}
let mut last_blink: u32 = 0; let mut last_blink: u32 = 0;
let mut toggle = false; let mut toggle = false;
@ -137,7 +135,7 @@ fn main() -> ! {
toggle = !toggle; toggle = !toggle;
write_led(if toggle { 1 } else { 0 }); write_led(if toggle { 1 } else { 0 });
let val: u32 = unsafe {read_reg(0x8000_2000)}; let val: u32 = unsafe { read_reg(0x8000_2000) };
} }
// TODO I think the timer might actually stop until the event is cleared? this may pose // TODO I think the timer might actually stop until the event is cleared? this may pose
@ -151,45 +149,45 @@ fn main() -> ! {
//if iface.poll(Instant::from_millis(now), &mut device, &mut socket_set) { //if iface.poll(Instant::from_millis(now), &mut device, &mut socket_set) {
//let sock = socket_set.get_mut::<TcpSocket>(command_socket); //let sock = socket_set.get_mut::<TcpSocket>(command_socket);
//if !sock.is_open() { //if !sock.is_open() {
// sock.listen(2000); // sock.listen(2000);
//} //}
//let mut echo_tx_buf = [0u8; 32]; //let mut echo_tx_buf = [0u8; 32];
//match sock.recv(|buf| { //match sock.recv(|buf| {
// if buf.len() > 0 { // if buf.len() > 0 {
// // Copy into send buffer // // Copy into send buffer
// let rd_len = core::cmp::min(buf.len(), echo_tx_buf.len()); // let rd_len = core::cmp::min(buf.len(), echo_tx_buf.len());
// &echo_tx_buf[..rd_len].copy_from_slice(&buf[..rd_len]); // &echo_tx_buf[..rd_len].copy_from_slice(&buf[..rd_len]);
// defmt::trace!("RX data command"); // defmt::trace!("RX data command");
// // Return slice to send // // Return slice to send
// (rd_len, Some(&echo_tx_buf[..rd_len])) // (rd_len, Some(&echo_tx_buf[..rd_len]))
// } else { // } else {
// (0, None) // (0, None)
// } // }
//}) { //}) {
// Err(_) => { // Err(_) => {
// // Close the socket, re-open it later // // Close the socket, re-open it later
// //sock.abort(); // //sock.abort();
// // Is doing this immediately legal? // // Is doing this immediately legal?
// //sock.listen(2000); // //sock.listen(2000);
// } // }
// // Some data to send // // Some data to send
// Ok(Some(tx_data)) => { // Ok(Some(tx_data)) => {
// match sock.send_slice(tx_data) { // match sock.send_slice(tx_data) {
// Err(_) => { // Err(_) => {
// //sock.abort(); // //sock.abort();
// //sock.listen(2000); // //sock.listen(2000);
// } // }
// _ => (), // _ => (),
// } // }
// } // }
// // No data to send // // No data to send
// Ok(None) => (), // Ok(None) => (),
//} //}
//} //}
} }
@ -206,7 +204,6 @@ fn handle_timer_event() {
write_reg(0xf000_3818, 1u32); write_reg(0xf000_3818, 1u32);
SECONDS += 1; SECONDS += 1;
} }
} }
fn busy_wait(ms: u32) { fn busy_wait(ms: u32) {
@ -217,8 +214,10 @@ fn busy_wait(ms: u32) {
// } // }
//} //}
for i in 0..ms*20_000 { for i in 0..ms * 20_000 {
unsafe {asm!("nop");} unsafe {
asm!("nop");
}
} }
} }

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@ -8,7 +8,7 @@
//! because the crc python package had it as well. //! because the crc python package had it as well.
//! //!
//! The 4 bytes of data are little-endian. //! The 4 bytes of data are little-endian.
//! //!
//! For the settings that can be set, see [Settings]. //! For the settings that can be set, see [Settings].
//! //!
//! ## Sending a command //! ## Sending a command