From a05af8739cf1883a8691b71d841f56da3fdf7add Mon Sep 17 00:00:00 2001
From: David Lenfesty <lenfesty@ualberta.ca>
Date: Fri, 24 Mar 2023 20:54:05 -0600
Subject: [PATCH] gateware: fix UART and connections

---
 gateware/main.py                    | 15 +++++++--------
 gateware/platforms/colorlight_i9.py |  2 +-
 2 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/gateware/main.py b/gateware/main.py
index 2c65742..0a7ea6b 100644
--- a/gateware/main.py
+++ b/gateware/main.py
@@ -143,7 +143,6 @@ class Core(Elaboratable):
         # Create CSR bus and connect it to Wishbone
         self.csr = csr.Decoder(addr_width=10, data_width=8)
         m.submodules.csr = self.csr
-        print(f"CSR bus added at 0x{start:08x}")
 
         # I2C (connected to DAC for VCO and ADC?)
         if platform is not None:
@@ -161,13 +160,11 @@ class Core(Elaboratable):
         print(f"LED added to CSR at 0x{i2c_start}")
 
         if platform is not None:
-            uart_pads = platform.request("uart")
+            uart_pads = platform.request("uart", 1)
         else:
-            uart_pads = type('UARTPads', (), {})
-            uart_pads.tx = Signal()
-            uart_pads.rx = Signal()
+            uart_pads = None
         # TODO spread sysclk freq through design
-        self.uart = uart.UART(50e6, 1152_000)
+        self.uart = uart.UART(50e6, 115_200, pins=uart_pads)
         m.submodules.uart = self.uart
         uart_start, _stop, _step = self.csr.add(self.uart.bus)
         print(f"UART added to CSR at 0x{uart_start:x}")
@@ -175,12 +172,13 @@ class Core(Elaboratable):
         self.csr_bridge = WishboneCSRBridge(self.csr.bus, data_width=32, name="CSR")
         m.submodules.csr_bridge = self.csr_bridge
         # TODO shouldn't have to hard-specify this address
-        start, _stop, _step = self.decoder.add(self.csr_bridge.wb_bus, addr=0x01003000)
+        start, _stop, _step = self.decoder.add(self.csr_bridge.wb_bus, addr=0x02000000)
+        print(f"CSR bus added at 0x{start:08x}")
 
         # Ethernet
         self.eth = LiteEth(self.eth_interface)
         m.submodules.eth = self.eth
-        #start, _stop, _step = self.decoder.add(self.eth, addr=0x02000000)
+        start, _stop, _step = self.decoder.add(self.eth, addr=0x03000000)
         print(f"LiteETH added at 0x{start:08x}")
 
         # Connect arbiter to decoder
@@ -199,6 +197,7 @@ class SoC(Elaboratable):
         pass
 
     def elaborate(self, platform):
+        # TODO pull I2C and UART into here instead of the "core"
         if platform is not None:
             clk25 = platform.request("clk25")
             led_signal = platform.request("led")
diff --git a/gateware/platforms/colorlight_i9.py b/gateware/platforms/colorlight_i9.py
index c86a727..0261a9b 100644
--- a/gateware/platforms/colorlight_i9.py
+++ b/gateware/platforms/colorlight_i9.py
@@ -98,7 +98,7 @@ class Colorlight_i9_Platform(LatticeECP5Platform):
 
         Resource("i2c", 0,
             Subsignal("sda", Pins("D16", dir="io")),
-            Subsignal("scl", Pins("F5", dir="o")),
+            Subsignal("scl", Pins("F5", dir="io")), # Hacky stuff for now, amlib needs it to be io for some reason
             Attrs(IO_TYPE="LVCMOS33")
         ),
     ]