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fw: eth testing and debug process

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This commit is contained in:
David Lenfesty 2023-04-22 13:39:32 -06:00
parent 29ec5a8a43
commit a864da5354
3 changed files with 69 additions and 46 deletions
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3
.gitmodules vendored
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@ -1,3 +1,6 @@
[submodule "gateware/jtagtap"] [submodule "gateware/jtagtap"]
path = gateware/jtagtap path = gateware/jtagtap
url = git@github.com:davidlenfesty/jtagtap url = git@github.com:davidlenfesty/jtagtap
[submodule "firmware/hello_world_c/litex"]
path = firmware/hello_world_c/litex
url = https://github.com/enjoy-digital/litex

1
firmware/hello_world_c/litex Submodule

@ -0,0 +1 @@
Subproject commit b367c27191511f36b10ec4103198978f86f9502c

111
firmware/src/eth.rs
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@ -29,12 +29,16 @@ const ETHMAC_SRAM_WRITER_EV_ENABLE: u32 = 0x814;
// Reader, or TX register blocks // Reader, or TX register blocks
const ETHMAC_SRAM_READER_START: u32 = 0x818; const ETHMAC_SRAM_READER_START: u32 = 0x818;
const ETHMAC_SRAM_READER_READY: u32 = 0x81c; const ETHMAC_SRAM_READER_READY: u32 = 0x81c;
const ETHMAC_SRAM_READER_LEVEL: u32 = 0x820;
const ETHMAC_SRAM_READER_SLOT: u32 = 0x824; const ETHMAC_SRAM_READER_SLOT: u32 = 0x824;
const ETHMAC_SRAM_READER_LENGTH: u32 = 0x828; const ETHMAC_SRAM_READER_LENGTH: u32 = 0x828;
const ETHMAC_SRAM_READER_EV_STATUS: u32 = 0x82c; const ETHMAC_SRAM_READER_EV_STATUS: u32 = 0x82c;
const ETHMAC_SRAM_READER_EV_PENDING: u32 = 0x830; const ETHMAC_SRAM_READER_EV_PENDING: u32 = 0x830;
const ETHMAC_SRAM_READER_EV_ENABLE: u32 = 0x834; const ETHMAC_SRAM_READER_EV_ENABLE: u32 = 0x834;
// Offset of ETHMAC SRAM from base
const ETHMAC_OFFSET: u32 = 0x0002_0000;
const NUM_RX_SLOTS: u32 = 2; const NUM_RX_SLOTS: u32 = 2;
const NUM_TX_SLOTS: u32 = 2; const NUM_TX_SLOTS: u32 = 2;
const MTU: usize = 1530; const MTU: usize = 1530;
@ -46,49 +50,52 @@ use crate::uart::AmlibUart;
use core::fmt::Write; use core::fmt::Write;
pub struct LiteEthDevice { pub struct LiteEthDevice {
base_addr: u32, csr_addr: u32,
ethmac_addr: u32,
} }
pub struct LiteEthTxToken { pub struct LiteEthTxToken {
pub base_addr: u32, pub csr_addr: u32,
pub ethmac_addr: u32,
pub slot: u32, pub slot: u32,
} }
pub struct LiteEthRxToken { pub struct LiteEthRxToken {
pub base_addr: u32, pub csr_addr: u32,
pub ethmac_addr: u32,
} }
impl LiteEthDevice { impl LiteEthDevice {
/// Initialises the device and returns an instance. Unsafe because there are /// Initialises the device and returns an instance. Unsafe because there are
/// no checks for other users. /// no checks for other users.
pub unsafe fn try_init(base_addr: u32) -> Option<Self> { pub unsafe fn try_init(csr_addr: u32, ethmac_addr: u32) -> Option<Self> {
if !LiteEthDevice::check_wishbone_access(base_addr) { if !LiteEthDevice::check_wishbone_access(csr_addr) {
return None; return None;
} }
// Reset liteeth // Reset liteeth
write_reg(base_addr + CTRL_RESET, 1u32); write_reg(csr_addr + CTRL_RESET, 1u32);
busy_wait(200); busy_wait(200);
write_reg(base_addr + CTRL_RESET, 0u32); write_reg(csr_addr + CTRL_RESET, 0u32);
busy_wait(200); busy_wait(200);
// Clear RX event to mark the slot as available // Clear RX event to mark the slot as available
write_reg(base_addr + ETHMAC_SRAM_WRITER_EV_PENDING, 1u32); write_reg(csr_addr + ETHMAC_SRAM_WRITER_EV_PENDING, 1u32);
// Clear TX event (unsure if necessary) // Clear TX event (unsure if necessary)
write_reg(base_addr + ETHMAC_SRAM_READER_EV_PENDING, 1u32); write_reg(csr_addr + ETHMAC_SRAM_READER_EV_PENDING, 1u32);
// Disable event interrupts, we poll, so no use for an interrupt // Disable event interrupts, we poll, so no use for an interrupt
write_reg(base_addr + ETHMAC_SRAM_READER_EV_ENABLE, 0u32); write_reg(csr_addr + ETHMAC_SRAM_READER_EV_ENABLE, 0u32);
write_reg(base_addr + ETHMAC_SRAM_WRITER_EV_ENABLE, 0u32); write_reg(csr_addr + ETHMAC_SRAM_WRITER_EV_ENABLE, 0u32);
// Return a new device // Return a new device
Some(Self { base_addr}) Some(Self { csr_addr, ethmac_addr })
} }
/// Checks that wishbone memory access is correct for the given base address /// Checks that wishbone memory access is correct for the given base address
unsafe fn check_wishbone_access(base_addr: u32) -> bool { unsafe fn check_wishbone_access(csr_addr: u32) -> bool {
// Read scratch register, which resets to 0x12345678 // Read scratch register, which resets to 0x12345678
let value: u32 = read_reg(base_addr + CTRL_SCRATCH); let value: u32 = read_reg(csr_addr + CTRL_SCRATCH);
// If this isn't true, we screwed. // If this isn't true, we screwed.
return value == 0x12345678; return value == 0x12345678;
@ -107,13 +114,13 @@ impl smoltcp::phy::Device for LiteEthDevice {
unsafe { unsafe {
// No data is available // No data is available
if read_reg::<u32>(self.base_addr + ETHMAC_SRAM_WRITER_EV_STATUS) == 0 { if read_reg::<u32>(self.csr_addr + ETHMAC_SRAM_WRITER_EV_STATUS) == 0 {
return None; return None;
} }
// Check if TX slot 1 is available for the "return" packet // Due to the fact that I can't check the status of an individual slot, I am going to just make sure
write_reg(self.base_addr + ETHMAC_SRAM_READER_SLOT, 1u32); // level is 0 before I hand out any TX tokens
if read_reg::<u32>(self.base_addr + ETHMAC_SRAM_READER_READY) != 1 { if read_reg::<u32>(self.csr_addr + ETHMAC_SRAM_READER_LEVEL) != 0 {
return None; return None;
} }
@ -123,10 +130,12 @@ impl smoltcp::phy::Device for LiteEthDevice {
defmt::trace!("RX Token given"); defmt::trace!("RX Token given");
Some(( Some((
LiteEthRxToken { LiteEthRxToken {
base_addr: self.base_addr, csr_addr: self.csr_addr,
ethmac_addr: self.ethmac_addr,
}, },
LiteEthTxToken { LiteEthTxToken {
base_addr: self.base_addr, csr_addr: self.csr_addr,
ethmac_addr: self.ethmac_addr,
slot: 1, slot: 1,
}, },
)) ))
@ -136,15 +145,17 @@ impl smoltcp::phy::Device for LiteEthDevice {
fn transmit(&mut self, _timestamp: smoltcp::time::Instant) -> Option<Self::TxToken<'_>> { fn transmit(&mut self, _timestamp: smoltcp::time::Instant) -> Option<Self::TxToken<'_>> {
// Check if slot 0 is ready, if so, return TxToken to slot 0 // Check if slot 0 is ready, if so, return TxToken to slot 0
unsafe { unsafe {
write_reg(self.base_addr + ETHMAC_SRAM_READER_SLOT, 0u32); // Due to the fact that I can't check the status of an individual slot, I am going to just make sure
if read_reg::<u32>(self.base_addr + ETHMAC_SRAM_READER_READY) == 0 { // level is 0 before I hand out any TX tokens
if read_reg::<u32>(self.csr_addr + ETHMAC_SRAM_READER_LEVEL) != 0 {
return None; return None;
} }
} }
//writeln!(self.uart, "TX tkn").unwrap(); defmt::trace!("TX token given");
Some(LiteEthTxToken { Some(LiteEthTxToken {
base_addr: self.base_addr, csr_addr: self.csr_addr,
ethmac_addr: self.ethmac_addr,
slot: 0, slot: 0,
}) })
} }
@ -167,23 +178,41 @@ impl smoltcp::phy::TxToken for LiteEthTxToken {
where where
F: FnOnce(&mut [u8]) -> R, F: FnOnce(&mut [u8]) -> R,
{ {
// TODO 0x800 is ETHMAC offset, need to encode it somehow properly let tx_slot_base: u32 = self.ethmac_addr + NUM_RX_SLOTS * SLOT_LEN;
let tx_slot_base: u32 = self.base_addr + 0x800 + NUM_RX_SLOTS * SLOT_LEN; let tx_slot_addr = tx_slot_base + 0 * SLOT_LEN;
let tx_slot_addr = tx_slot_base + (self.slot as u32) * SLOT_LEN;
let tx_slot: &mut [u8] = let tx_slot: &mut [u8] =
unsafe { core::slice::from_raw_parts_mut(tx_slot_addr as *mut u8, MTU) }; unsafe { core::slice::from_raw_parts_mut(tx_slot_addr as *mut u8, len) };
unsafe {
// Wait for it to be ready?
while read_reg::<u32>(self.csr_addr + ETHMAC_SRAM_READER_READY) == 0 {}
}
// Write data to buffer // Write data to buffer
let res = f(tx_slot); let res = f(tx_slot);
// Write length, and start sending data // Write length, and start sending data
unsafe { unsafe {
let level = read_reg::<u32>(self.csr_addr + ETHMAC_SRAM_READER_LEVEL);
defmt::trace!("level before sending: {}", level);
// set slot // set slot
write_reg(self.base_addr + ETHMAC_SRAM_READER_SLOT, self.slot); write_reg(self.csr_addr + ETHMAC_SRAM_READER_SLOT, 0u32);
// set length // set length
write_reg(self.base_addr + ETHMAC_SRAM_READER_LENGTH, len as u32); write_reg(self.csr_addr + ETHMAC_SRAM_READER_LENGTH, len as u32);
let slot = read_reg::<u32>(self.csr_addr + ETHMAC_SRAM_READER_SLOT);
let length = read_reg::<u32>(self.csr_addr + ETHMAC_SRAM_READER_LENGTH);
defmt::trace!("slot: {}, len: {}, addr: 0x{:08x}", slot, len, tx_slot_addr);
// send data // send data
write_reg(self.base_addr + ETHMAC_SRAM_READER_START, 1u32); write_reg(self.csr_addr + ETHMAC_SRAM_READER_START, 1u32);
let level = read_reg::<u32>(self.csr_addr + ETHMAC_SRAM_READER_LEVEL);
defmt::trace!("level after sending: {}", level);
// Clear event because why tf not
write_reg(self.csr_addr + ETHMAC_SRAM_READER_EV_PENDING, 1u32);
} }
res res
@ -197,34 +226,24 @@ impl smoltcp::phy::RxToken for LiteEthRxToken {
{ {
// Read the slot number // Read the slot number
let slot = unsafe { let slot = unsafe {
read_reg::<u32>(self.base_addr + ETHMAC_SRAM_WRITER_SLOT) read_reg::<u32>(self.csr_addr + ETHMAC_SRAM_WRITER_SLOT)
}; };
// Read the available length // Read the available length
let len = unsafe { let len = unsafe {
read_reg::<u32>(self.base_addr + ETHMAC_SRAM_WRITER_LENGTH) read_reg::<u32>(self.csr_addr + ETHMAC_SRAM_WRITER_LENGTH)
}; };
// TODO 0x800 is ETHMAC offset, need to encode it somehow properly let rx_slot_addr: u32 = self.ethmac_addr + slot * SLOT_LEN;
let rx_slot_base: u32 = self.base_addr + 0x800 + SLOT_LEN;
let rx_slot_addr: u32 = rx_slot_base + slot * SLOT_LEN;
let rx_slot: &mut [u8] = let rx_slot: &mut [u8] =
unsafe { core::slice::from_raw_parts_mut(rx_slot_addr as *mut u8, len as usize) }; unsafe { core::slice::from_raw_parts_mut(rx_slot_addr as *mut u8, len as usize) };
defmt::trace!("RX packet data. slot: {}, len: {}, addr: 0x{:08x}", slot, len, rx_slot_addr); defmt::trace!("rx: len {}, addr: 0x{:08x}", len, rx_slot_addr);
for i in 0..16 {
let base = self.base_addr + i * 0x400;
defmt::trace!("Data at offset: 0x{:08x}", base);
for j in 0..32 {
defmt::trace!("byte {}: 0x{:x}", j, unsafe {read_reg::<u8>(base + j)});
}
}
// Read data from buffer // Read data from buffer
let res = f(rx_slot); let res = f(rx_slot);
// Clear event to mark slot as available // Clear event to mark slot as available
unsafe { unsafe {
write_reg(self.base_addr + ETHMAC_SRAM_WRITER_EV_PENDING, 1u32); write_reg(self.csr_addr + ETHMAC_SRAM_WRITER_EV_PENDING, 1u32);
} }
res res