From aebb3a58f01fef362a68b561801cdbbe9d3bf7ee Mon Sep 17 00:00:00 2001
From: David Lenfesty <lenfesty@ualberta.ca>
Date: Sat, 27 May 2023 13:30:01 -0600
Subject: [PATCH] gw: add ADC2-4 pinouts and update changed pins

---
 gateware/platforms/sonar.py | 45 ++++++++++++++++++++++++++++++-------
 1 file changed, 37 insertions(+), 8 deletions(-)

diff --git a/gateware/platforms/sonar.py b/gateware/platforms/sonar.py
index fd84aa8..0232783 100644
--- a/gateware/platforms/sonar.py
+++ b/gateware/platforms/sonar.py
@@ -19,7 +19,7 @@ from litex.build.lattice.programmer import EcpDapProgrammer
 
 # IOs ----------------------------------------------------------------------------------------------
 
-_io_v7_0 = [ # Documented by @smunaut
+_io_v7_0 = [ # Colorlight i9 documented by @smunaut
     # Clk
     ("clk25", 0, Pins("P3"), IOStandard("LVCMOS33")),
 
@@ -117,13 +117,42 @@ _io_v7_0 = [ # Documented by @smunaut
 
     # High speed parallel ADCs
     ("adc", 0,
-        Subsignal("data", Pins("M18 N18 N17 P18 U17 U18 T17 M17 P17 R17")),
-        # TODO ???? what other pins are changed in 7.2
-        Subsignal("refclk", Pins("L2")),
-        Subsignal("oen_b", Pins("K18")),
-        Subsignal("standby", Pins("C18")),
-        Subsignal("dfs", Pins("T18")),
-        Subsignal("otr", Pins("R18")),
+        # Rev A pins
+        #Subsignal("data", Pins("M18 N18 N17 P18 U17 U18 T17 M17 P17 R17")),
+        # Rev B pins
+        Subsignal("data", Pins("L20 M18 N18 N17 P18 U17 U18 T17 M17 P17")),
+        Subsignal("refclk", Pins("K18")),
+        Subsignal("oen_b", Pins("C18")),
+        Subsignal("standby", Pins("T18")),
+        Subsignal("dfs", Pins("R18")),
+        Subsignal("otr", Pins("R17")),
+        IOStandard("LVCMOS33")
+    ),
+    ("adc", 1,
+        Subsignal("data", Pins("R1 T1 U1 Y2 W1 V1 M1 N2 N3 T2")),
+        Subsignal("refclk", Pins("M4")),
+        Subsignal("oen_b", Pins("N4")),
+        Subsignal("standby", Pins("R3")),
+        Subsignal("dfs", Pins("T3")),
+        Subsignal("otr", Pins("M3")),
+        IOStandard("LVCMOS33")
+    ),
+    ("adc", 2,
+        Subsignal("data", Pins("A18 C17 A19 B18 B19 B20 C20 D19 D20 E19")),
+        Subsignal("refclk", Pins("J19")),
+        Subsignal("oen_b", Pins("H20")),
+        Subsignal("standby", Pins("G20")),
+        Subsignal("dfs", Pins("G19")),
+        Subsignal("otr", Pins("F20")),
+        IOStandard("LVCMOS33")
+    ),
+    ("adc", 3,
+        Subsignal("data", Pins("E4 F1 F3 G3 H3 H4 H5 J4 J5 K3")),
+        Subsignal("refclk", Pins("M4")),
+        Subsignal("oen_b", Pins("N4")),
+        Subsignal("standby", Pins("B3")),
+        Subsignal("dfs", Pins("K5")),
+        Subsignal("otr", Pins("K4")),
         IOStandard("LVCMOS33")
     ),
 ]