From afa95aa32e4fdd054dfe6004532f47c388181c24 Mon Sep 17 00:00:00 2001 From: David Lenfesty Date: Fri, 16 Jun 2023 16:33:07 -0600 Subject: [PATCH] fw: clean up some timer things in main --- firmware/src/main.rs | 31 +++---------------------------- 1 file changed, 3 insertions(+), 28 deletions(-) diff --git a/firmware/src/main.rs b/firmware/src/main.rs index c9d1c86..fb16b63 100644 --- a/firmware/src/main.rs +++ b/firmware/src/main.rs @@ -93,36 +93,17 @@ fn main() -> ! { sock.set_timeout(Some(Duration::from_secs(10))) } - let mut logger_tx_storage = [0u8; 128]; - let mut logger_rx_storage = [0u8; 16]; - let mut logger_tx_buf = SocketBuffer::new(&mut logger_tx_storage[..]); - let mut logger_rx_buf = SocketBuffer::new(&mut logger_rx_storage[..]); - let mut logger_socket = socket_set.add(TcpSocket::new(logger_tx_buf, logger_rx_buf)); - - unsafe { - logging::set_logger_socket(Some(socket_set.get_mut::(logger_socket))); - } - let mut last_blink: u32 = 0; let mut toggle = false; //defmt::info!("Done setup"); + // Set up timer for polling events unsafe { - //riscv::interrupt::enable(); - //riscv::register::mie::set_mext(); - //riscv::register::mie::set_msoft(); - - // Enable UART rx event for test - //write_reg(0xf000_4014, 1u32); - // Timer stuff write_reg(0xf000_3808, 0u32); // Disable timer write_reg(0xf000_3800, 0u32); // Set LOAD value write_reg(0xf000_3804, 60_000_000u32); // Set RELOAD value write_reg(0xf000_3808, 1u32); // Enable timer - - // Enable timer event - //write_reg(0xf000_381c, 1u32); } let mut cmd = command_interface::CommandInterface::new(); @@ -207,14 +188,8 @@ fn handle_timer_event() { } fn busy_wait(ms: u32) { - //let start = millis(); - //while millis() - start < ms { - // unsafe { - // asm!("nop"); - // } - //} - - for i in 0..ms * 20_000 { + let start = millis(); + while millis() - start < ms { unsafe { asm!("nop"); }