firmware: i2c work, not finished
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@ -7,12 +7,10 @@
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// Using the blocking API because the peripheral requires fairly tight timing to operate
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// correctly, and I don't feel like writing the gateware to resolve that.
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use embedded_hal::blocking::i2c::{Write, Read, SevenBitAddress, Transactional, Operation};
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use embedded_hal::blocking::i2c::{Write, Read, SevenBitAddress};
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use crate::{read_reg, write_reg};
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use core::arch::asm;
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// TODO I think there may be bus address semantics I'm not 100% on.
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// There's a possiblity these addresses are wrong, and they need to be 4 bytes each
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const CR: u32 = 0;
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const SR: u32 = 1;
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const DWR: u32 = 2;
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@ -30,18 +28,24 @@ pub struct AmlibI2c {
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base_addr: u32,
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}
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impl AmlibI2c {
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use core::fmt::Write as _;
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impl AmlibI2c{
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pub fn new(base_addr: u32) -> Self {
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AmlibI2c { base_addr }
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}
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fn wait_while_busy(&self) {
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fn wait_while_busy(&mut self) {
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unsafe {
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while read_reg::<u32>(self.base_addr + SR) & 1 != 0 {
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while read_reg::<u8>(self.base_addr + SR) & 1 != 0 {
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asm!("nop");
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}
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}
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}
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fn is_nack(&self) -> bool {
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unsafe { read_reg::<u8>(self.base_addr + SR) & 0x02 != 0 }
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}
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}
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impl Write<SevenBitAddress> for AmlibI2c {
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@ -50,34 +54,40 @@ impl Write<SevenBitAddress> for AmlibI2c {
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fn write(&mut self, address: SevenBitAddress, bytes: &[u8]) -> Result<(), Self::Error> {
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unsafe {
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if (read_reg::<u32>(self.base_addr + SR) & 1) != 0 {
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if (read_reg::<u8>(self.base_addr + SR) & 1) != 0 {
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return Err(Error::Busy);
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}
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// START
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write_reg(self.base_addr + CR, 0x01u32);
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// Pre-load data w/ address (R/~W = 0)
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write_reg(self.base_addr + DWR, (address << 1) as u32);
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write_reg(self.base_addr + CR, 0x01u8);
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self.wait_while_busy();
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// Send address byte
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write_reg(self.base_addr + CR, 0x04u32);
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if read_reg::<u32>(self.base_addr + SR) & 0x02 != 0 {
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// Send address byte (R/~W = 0)
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write_reg(self.base_addr + DWR, address << 1);
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write_reg(self.base_addr + CR, 0x04u8);
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self.wait_while_busy();
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// Check NACK
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if self.is_nack() {
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return Err(Error::Nack);
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}
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// Write data
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for byte in bytes {
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// Write byte
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write_reg(self.base_addr + DWR, *byte as u32);
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write_reg(self.base_addr + DWR, *byte);
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// Send byte
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write_reg(self.base_addr + CR, 0x04u8);
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self.wait_while_busy();
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// Send byte once done sending the last byte
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write_reg(self.base_addr + CR, 0x04u32);
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if self.is_nack() {
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return Err(Error::Nack);
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}
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}
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self.wait_while_busy();
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// STOP
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write_reg(self.base_addr + CR, 0x02u32);
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write_reg(self.base_addr + CR, 0x02u8);
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self.wait_while_busy();
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Ok(())
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@ -90,15 +100,46 @@ impl Read<SevenBitAddress> for AmlibI2c {
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type Error = Error;
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fn read(&mut self, address: SevenBitAddress, buffer: &mut [u8]) -> Result<(), Self::Error> {
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unsafe {
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if (read_reg::<u8>(self.base_addr + SR) & 1) != 0 {
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return Err(Error::Busy);
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}
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// START
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write_reg(self.base_addr + CR, 0x01u8);
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self.wait_while_busy();
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// Send address byte (R/~W = 1)
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write_reg(self.base_addr + DWR, (address << 1) + 1);
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write_reg(self.base_addr + CR, 0x04u8);
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self.wait_while_busy();
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if self.is_nack() {
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return Err(Error::Nack);
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}
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for byte in buffer {
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// Start reading in a byte
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write_reg(self.base_addr + CR, 0x08u8);
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self.wait_while_busy();
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// Value is available once busy is clear
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*byte = read_reg::<u8>(self.base_addr + DRR);
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}
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// STOP
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write_reg(self.base_addr + CR, 0x02u8);
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Ok(())
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}
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}
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}
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impl Transactional for AmlibI2c {
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type Error = Error;
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fn exec<'a>(&mut self, address: u8, operations: &mut [Operation<'a>])
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-> Result<(), Self::Error> {
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Ok(())
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}
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}
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// I don't need this for MCP4726
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//impl Transactional for AmlibI2c {
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// type Error = Error;
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//
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// fn exec<'a>(&mut self, address: u8, operations: &mut [Operation<'a>])
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// -> Result<(), Self::Error> {
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// Ok(())
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// }
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//}
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@ -3,15 +3,16 @@
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extern crate panic_halt;
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use core::{arch::asm, ptr::{write, read}};
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use core::{arch::asm, ptr::{write_volatile, read_volatile}};
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use core::fmt::Write;
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use embedded_hal::prelude::_embedded_hal_blocking_i2c_Write;
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use embedded_hal::prelude::{_embedded_hal_blocking_i2c_Write, _embedded_hal_blocking_i2c_Read};
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use riscv_rt::entry;
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mod eth;
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mod i2c;
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mod uart;
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mod mcp4726;
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// use `main` as the entry point of this application
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// `main` is not allowed to return
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@ -28,15 +29,29 @@ fn main() -> ! {
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//};
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let blink_period = 10_000_000u32;
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//let mut i2c = i2c::AmlibI2c::new(0x0200_0000);
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//let data = [0u8, 2u8];
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//i2c.write(0xAA, &data).unwrap();
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let mut uart = uart::AmlibUart::new(0x0200_0040);
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// Configure DAC
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let mut i2c = i2c::AmlibI2c::new(0x0200_0000);
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//let mut buf = [0u8; 1];
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//i2c.read(0b110_0011, &mut buf);
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let mut dac = mcp4726::MCP4726::new(3);
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writeln!(uart, "Reading DAC status");
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dac.read_status(&mut i2c).unwrap();
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writeln!(uart, "Configuring DAC");
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dac.write_config(&mut i2c, mcp4726::Config {
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vref_source: mcp4726::VRef::UnbufferedVRef,
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operation: mcp4726::PowerDown::NormalOperation,
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use_2x_gain: false,
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}).unwrap();
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writeln!(uart, "Setting DAC");
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dac.write_dac(&mut i2c, 0x0800).unwrap();
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loop {
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//eth::tranmsit();
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uart.write_str("Hello world!\r\n");
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//writeln!(uart, "Hello world!");
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write_led(0);
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busy_wait(blink_period);
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write_led(1);
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@ -57,9 +72,9 @@ fn write_led(val: u32) {
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}
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unsafe fn write_reg<T>(addr: u32, value: T) {
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write(addr as *mut T, value);
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write_volatile(addr as *mut T, value);
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}
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unsafe fn read_reg<T>(addr: u32) -> T {
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return read(addr as *mut T);
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return read_volatile(addr as *mut T);
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}
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133
firmware/src/mcp4726.rs
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133
firmware/src/mcp4726.rs
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@ -0,0 +1,133 @@
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//! Blocking driver for MCP2746
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use embedded_hal::blocking::i2c::{Write, Read};
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const COMMAND_WRITE_VOLATILE_DAC: u8 = 0x00;
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const COMMAND_WRITE_VOLATILE_MEM: u8 = 0x40;
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const COMMAND_WRITE_ALL_MEM: u8 = 0x60;
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const COMMAND_WRITE_VOLATILE_CONFIG: u8 = 0x80;
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const BASE_ADDRESS: u8 = 0b110_0000;
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum VRef {
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UnbufferedVDD,
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UnbufferedVRef,
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BufferedVRef,
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}
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum PowerDown {
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NormalOperation,
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PoweredDownVout1k,
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PoweredDownVout100k,
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PoweredDownVout500k,
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}
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/// Configuration to apply
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub struct Config {
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pub vref_source: VRef,
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/// Set device operation
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pub operation: PowerDown,
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/// True to set gain 2x, false for 1x
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pub use_2x_gain: bool,
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}
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub struct Status {
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/// Is the device ready to use? Only false in an EEPROM programming cycle
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pub ready: bool,
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/// Power-on reset status indicator. Low if VDD is below the minimum operational
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/// voltage.
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pub device_powered: bool,
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}
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pub struct MCP4726 {
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address: u8,
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power_status: PowerDown,
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}
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impl MCP4726 {
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pub fn new(sub_address: u8) -> Self {
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Self {
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address: BASE_ADDRESS + (sub_address & 0x07),
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// TODO maybe come up with better semantics for setting this on init
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power_status: PowerDown::NormalOperation,
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}
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}
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pub fn read_status<Error>(&self, i2c: &mut dyn Read<Error = Error>) -> Result<Status, Error> {
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let mut buf = [0u8; 1];
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self.read_all_mem(i2c, &mut buf)?;
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Ok(Status {
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ready: buf[0] & 0x80 != 0,
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device_powered: buf[0] & 0x40 != 0,
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})
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}
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pub fn write_config<Error>(&mut self, i2c: &mut dyn Write<Error = Error>, config: Config) -> Result<(), Error> {
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let mut buf = [0u8; 1];
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buf[0] |= COMMAND_WRITE_VOLATILE_CONFIG;
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buf[0] |= MCP4726::vref_config(config.vref_source) << 3;
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buf[0] |= MCP4726::power_config(config.operation) << 1;
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if config.use_2x_gain {
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buf[0] |= 1;
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}
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// Make sure power config is set properly
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self.power_status = config.operation;
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i2c.write(self.address, &buf)?;
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Ok(())
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}
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pub fn write_dac<Error>(&self, i2c: &mut dyn Write<Error = Error>, dac: u16) -> Result<(), Error> {
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let mut buf = [0u8; 2];
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buf[0] |= COMMAND_WRITE_VOLATILE_DAC;
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// Note this "overlaps" the command bits, the lowest command bit is not used for this one
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buf[0] |= MCP4726::power_config(self.power_status) << 4;
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buf[0] |= (dac >> 8) as u8 & 0x0F;
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buf[1] = (dac & 0xFF) as u8;
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i2c.write(self.address, &buf)?;
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Ok(())
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}
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pub fn write_nonvolatile<Error>(&mut self, i2c: &mut dyn Write<Error = Error>, config: Config, dac: u16) -> Result<(), Error> {
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todo!()
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}
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/// Reads all memory, up to 6 bytes into the out buffer.
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fn read_all_mem<Error>(&self, i2c: &mut dyn Read<Error = Error>, out: &mut [u8]) -> Result<u8, Error> {
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let buf = if out.len() <= 6 {
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out
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} else {
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&mut out[0..6]
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};
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i2c.read(self.address, buf)?;
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Ok(buf.len() as u8)
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}
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fn vref_config(vref: VRef) -> u8 {
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match vref {
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VRef::UnbufferedVDD => 0b00,
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VRef::UnbufferedVRef => 0b10,
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VRef::BufferedVRef => 0b11,
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}
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}
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fn power_config(pd: PowerDown) -> u8 {
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match pd {
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PowerDown::NormalOperation => 0b00,
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PowerDown::PoweredDownVout1k => 0b01,
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PowerDown::PoweredDownVout100k => 0b10,
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PowerDown::PoweredDownVout500k => 0b11,
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}
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}
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}
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@ -10,10 +10,10 @@ const REG_DIVISOR_OFFSET: u32 = 0;
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const REG_SR_OFFSET: u32 = 2;
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const REG_DR_OFFSET: u32 = 3;
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pub const FLAG_SR_TX_FULL: u8 = (1 << 0);
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pub const FLAG_SR_TX_EMPTY: u8 = (1 << 1);
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pub const FLAG_SR_RX_FULL: u8 = (1 << 2);
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pub const FLAG_SR_RX_EMPTY: u8 = (1 << 3);
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const FLAG_SR_TX_FULL: u8 = 1 << 0;
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const FLAG_SR_TX_EMPTY: u8 = 1 << 1;
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const FLAG_SR_RX_FULL: u8 = 1 << 2;
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const FLAG_SR_RX_EMPTY: u8 = 1 << 3;
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pub enum Error {
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TxFull,
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