gateware: move back to LiteX
Had too many issues with integrating LiteEth. I put my FW into a LiteX SoC and it worked, so I migrated back. With the knowledge I gained doing Amaranth I could fix the issues I had adding a wishbone slave device pretty easily.
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gateware/litex_main.py
Executable file
199
gateware/litex_main.py
Executable file
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Kazumoto Kojima <kkojima@rr.iij4u.or.jp>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.io import DDROutput
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#from litex_boards.platforms import colorlight_i5
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from platforms import sonar as colorlight_i5
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoHDMIPHY
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from litex.soc.cores.led import LedChaser
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from litex.soc.interconnect.csr import *
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from litedram.modules import M12L64322A # Compatible with EM638325-6H.
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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from sampler import Sampler
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from litex.soc.integration.soc import SoCRegion
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, use_internal_osc=False, with_usb_pll=False, with_video_pll=False, sdram_rate="1:1"):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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if sdram_rate == "1:2":
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_ps = ClockDomain()
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else:
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self.clock_domains.cd_sys_ps = ClockDomain()
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# # #
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# Clk / Rst
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if not use_internal_osc:
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clk = platform.request("clk25")
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clk_freq = 25e6
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else:
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clk = Signal()
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div = 5
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self.specials += Instance("OSCG",
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p_DIV = div,
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o_OSC = clk
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)
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clk_freq = 310e6/div
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#rst_n = platform.request("cpu_reset_n")
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk, clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
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# SDRAM clock
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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# TODO make my own platform for this based on the colorlight one, so I can export I2C and other pins
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=60e6, eth_phy=0, with_led_chaser=True, use_internal_osc=False,
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sdram_rate="1:1", with_video_terminal=False, with_video_framebuffer=False,
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**kwargs):
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# TODO change SRAM size
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kwargs["integrated_sram_size"] = 64 * 1024
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kwargs["integrated_rom_init"] = "../firmware/fw.bin"
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platform = colorlight_i5.Platform(board="i9", revision="7.2", toolchain="trellis")
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# CRG --------------------------------------------------------------------------------------
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with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
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with_video_pll = with_video_terminal or with_video_framebuffer
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self.submodules.crg = _CRG(platform, sys_clk_freq,
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use_internal_osc = use_internal_osc,
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with_usb_pll = with_usb_pll,
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with_video_pll = with_video_pll,
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sdram_rate = sdram_rate
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)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, int(sys_clk_freq), ident = "LiteX SoC on Sonar FPGA", **kwargs)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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ledn = platform.request_all("user_led_n")
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self.submodules.leds = LedChaser(pads=ledn, sys_clk_freq=sys_clk_freq)
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# SPI Flash --------------------------------------------------------------------------------
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from litespi.modules import W25Q64 as SpiFlashModule
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=SpiFlashModule(Codes.READ_1_1_1))
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# SDR SDRAM --------------------------------------------------------------------------------
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#if not self.integrated_main_ram_size:
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# sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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# self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
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# self.add_sdram("sdram",
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# phy = self.sdrphy,
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# module = M12L64322A(sys_clk_freq, sdram_rate),
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# l2_cache_size = kwargs.get("l2_size", 8192)
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# )
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# Ethernet / Etherbone ---------------------------------------------------------------------
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks", eth_phy),
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pads = self.platform.request("eth", eth_phy),
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tx_delay = 0)
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self.add_ethernet(phy=self.ethphy)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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self.submodules.sampler = Sampler(platform.request("adc"))
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sampler_region = SoCRegion(origin=None, size=0x1000, cached=False)
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#self.add_wb_slave(0x9000_0000, self.sampler.bus, 0x1000)
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# TODO better way to do this?
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self.bus.add_slave(name="sampler", slave=self.sampler.bus, region=sampler_region)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Colorlight I5")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency.")
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sdopts = target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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target_group.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
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target_group.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator.")
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target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
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viopts = target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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# Build firmware
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import subprocess as sp
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sp.run(["./build_and_strip.sh"], cwd="../firmware").check_returncode()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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eth_phy = args.eth_phy,
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use_internal_osc = args.use_internal_osc,
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sdram_rate = args.sdram_rate,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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**soc_core_argdict(args)
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)
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soc.platform.add_extension(colorlight_i5._sdcard_pmod_io)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args)
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if args.build:
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builder.build(**builder_kargs)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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233
gateware/platforms/sonar.py
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233
gateware/platforms/sonar.py
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"""
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LiteX Platform for sonar board using Colorlight i9 module
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"""
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# This file used to belong to LiteX Boards
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#
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# Copyright (c) 2021 Kazumoto Kojima <kkojima@rr.iij4u.or.jp>
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# Copyright (c) 2023 David Lenfesty <lenfesty@ualberta.ca>
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# SPDX-License-Identifier: BSD-2-Clause
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# The Colorlight i5 PCB and IOs have been documented by @wuxx
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# https://github.com/wuxx/Colorlight-FPGA-Projects
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import copy
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import EcpDapProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io_v7_0 = [ # Documented by @smunaut
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# Clk
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("clk25", 0, Pins("P3"), IOStandard("LVCMOS33")),
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# Led
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("user_led_n", 0, Pins("U16"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("P16")),
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Subsignal("rx", Pins("L5")),
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IOStandard("LVCMOS33")
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),
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# TODO the other serial ports
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# TODO I2C
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# SPIFlash (GD25Q16CSIG)
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("spiflash", 0,
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Subsignal("cs_n", Pins("R2")),
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# https://github.com/m-labs/nmigen-boards/pull/38
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#Subsignal("clk", Pins("")), driven through USRMCLK
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Subsignal("mosi", Pins("W2")),
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Subsignal("miso", Pins("V2")),
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IOStandard("LVCMOS33"),
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),
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# SDRAM SDRAM (EM638325-6H)
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("sdram_clock", 0, Pins("B9"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"B13 C14 A16 A17 B16 B15 A14 A13",
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"A12 A11 B12")),
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Subsignal("dq", Pins(
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"D15 E14 E13 D12 E12 D11 C10 B17",
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"B8 A8 C7 A7 A6 B6 A5 B5",
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"D5 C5 D6 C6 E7 D7 E8 D8",
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"E9 D9 E11 C11 C12 D13 D14 C15")),
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Subsignal("we_n", Pins("A10")),
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Subsignal("ras_n", Pins("B10")),
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Subsignal("cas_n", Pins("A9")),
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#Subsignal("cs_n", Pins("")), # gnd
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#Subsignal("cke", Pins("")), # 3v3
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Subsignal("ba", Pins("B11 C8")), # sdram pin BA0 and BA1
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#Subsignal("dm", Pins("")), # gnd
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IOStandard("LVCMOS33"),
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Misc("SLEWRATE=FAST")
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),
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# RGMII Ethernet (B50612D)
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# The order of the two PHYs is swapped with the naming of the connectors
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# on the board so to match with the configuration of their PHYA[0] pins.
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("eth_clocks", 0,
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Subsignal("tx", Pins("G1")),
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Subsignal("rx", Pins("H2")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("P4")),
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Subsignal("mdio", Pins("P5")),
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Subsignal("mdc", Pins("N5")),
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Subsignal("rx_ctl", Pins("P2")),
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Subsignal("rx_data", Pins("K2 L1 N1 P1")),
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Subsignal("tx_ctl", Pins("K1")),
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Subsignal("tx_data", Pins("G2 H1 J1 J3")),
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IOStandard("LVCMOS33")
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),
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("eth_clocks", 1,
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Subsignal("tx", Pins("U19")),
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Subsignal("rx", Pins("L19")),
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IOStandard("LVCMOS33")
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),
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("eth", 1,
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Subsignal("rst_n", Pins("P4")),
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Subsignal("mdio", Pins("P5")),
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Subsignal("mdc", Pins("N5")),
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Subsignal("rx_ctl", Pins("M20")),
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Subsignal("rx_data", Pins("P20 N19 N20 M19")),
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Subsignal("tx_ctl", Pins("P19")),
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Subsignal("tx_data", Pins("U20 T19 T20 R20")),
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IOStandard("LVCMOS33")
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),
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# GPDI
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("gpdi", 0,
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Subsignal("clk_p", Pins("J19"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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#Subsignal("clk_n", Pins("K19"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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Subsignal("data0_p", Pins("G19"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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#Subsignal("data0_n", Pins("H20"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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Subsignal("data1_p", Pins("E20"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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#Subsignal("data1_n", Pins("F19"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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Subsignal("data2_p", Pins("C20"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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#Subsignal("data2_n", Pins("D19"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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),
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# High speed parallel ADCs
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("adc", 0,
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Subsignal("data", Pins("M18 N18 N17 P18 U17 U18 T17 M17 P17 R17")),
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# TODO ???? what other pins are changed in 7.2
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Subsignal("refclk", Pins("L2")),
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Subsignal("oen_b", Pins("K18")),
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Subsignal("standby", Pins("C18")),
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Subsignal("dfs", Pins("T18")),
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Subsignal("otr", Pins("R18")),
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IOStandard("LVCMOS33")
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),
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]
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# From https://github.com/wuxx/Colorlight-FPGA-Projects/blob/master/schematic/i5_v6.0-extboard.pdf and
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# https://github.com/wuxx/Colorlight-FPGA-Projects/blob/master/doc/i5_extboard_v1.2_pinout.png
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_connectors_v7_0 = [
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("pmode", "C17 B18 B20 F20 A18 A19 B19 D20"),
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("pmodf", "D1 C1 C2 E3 E2 D2 B1 A3"),
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]
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# ColorLight i9 V 7.2 hardware
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# See https://github.com/wuxx/Colorlight-FPGA-Projects/blob/master/colorlight_i9_v7.2.md
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# SPIFlash (W25Q64JVSIQ)
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_io_v7_2 = copy.deepcopy(_io_v7_0)
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# Change the LED pin to "L2"
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for i, x in enumerate(_io_v7_2):
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if x[:2] == ("user_led_n", 0):
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# TODO fix in HW
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#_io_v7_2[i] = ("user_led_n", 0, Pins("L2"), IOStandard("LVCMOS33"))
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_io_v7_2[i] = ("user_led_n", 0, Pins("J19"), IOStandard("LVCMOS33"))
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break
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# optional, alternative uart location
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# requires "--uart-name serialx"
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_io_v7_2 += [
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("serialx", 0, Subsignal("tx", Pins("E5")), Subsignal("rx", Pins("F4")), IOStandard("LVCMOS33"))
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]
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_connectors_v7_2 = copy.deepcopy(_connectors_v7_0)
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# Append the rest of the pmod interfaces
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_connectors_v7_2 += [
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# P2
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("pmodc", "P17 R18 C18 L2 M17 R17 T18 K18"),
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("pmodd", "J20 L18 M18 N17 G20 K20 L20 N18"),
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# P4
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("pmodg", "H4 G3 F1 F2 H3 F3 E4 E1"),
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("pmodh", "- E19 B3 K5 - B2 K4 A2"),
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# P5
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("pmodi", "D18 G5 F5 E5 D17 D16 E6 F4"),
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("pmodj", "J17 H17 H16 G16 H18 G18 F18 E18"),
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# P6
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("pmodk", "R3 M4 L5 J16 N4 L4 P16 J18"),
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("pmodl", "R1 U1 W1 M1 T1 Y2 V1 N2"),
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]
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# PMODS --------------------------------------------------------------------------------------------
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def sdcard_pmod_io(pmod):
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return [
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# SDCard PMOD:
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# - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
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("spisdcard", 0,
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Subsignal("clk", Pins(f"{pmod}:3")),
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Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULLMODE=UP")),
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Subsignal("cs_n", Pins(f"{pmod}:0"), Misc("PULLMODE=UP")),
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Subsignal("miso", Pins(f"{pmod}:2"), Misc("PULLMODE=UP")),
|
||||
Misc("SLEWRATE=FAST"),
|
||||
IOStandard("LVCMOS33"),
|
||||
),
|
||||
("sdcard", 0,
|
||||
Subsignal("data", Pins(f"{pmod}:2 {pmod}:4 {pmod}:5 {pmod}:0"), Misc("PULLMODE=UP")),
|
||||
Subsignal("cmd", Pins(f"{pmod}:1"), Misc("PULLMODE=UP")),
|
||||
Subsignal("clk", Pins(f"{pmod}:3")),
|
||||
Subsignal("cd", Pins(f"{pmod}:6")),
|
||||
#Misc("SLEWRATE=FAST"),
|
||||
IOStandard("LVCMOS33"),
|
||||
),
|
||||
]
|
||||
_sdcard_pmod_io = sdcard_pmod_io("pmode") # SDCARD PMOD on P3.
|
||||
|
||||
# Platform -----------------------------------------------------------------------------------------
|
||||
|
||||
class Platform(LatticePlatform):
|
||||
default_clk_name = "clk25"
|
||||
default_clk_period = 1e9/25e6
|
||||
|
||||
def __init__(self, board="i5", revision="7.0", toolchain="trellis"):
|
||||
if board == "i5":
|
||||
assert revision in ["7.0"]
|
||||
self.revision = revision
|
||||
device = {"7.0": "LFE5U-25F-6BG381C"}[revision]
|
||||
io = {"7.0": _io_v7_0}[revision]
|
||||
connectors = {"7.0": _connectors_v7_0}[revision]
|
||||
if board == "i9":
|
||||
assert revision in ["7.2"]
|
||||
self.revision = revision
|
||||
device = {"7.2": "LFE5U-45F-6BG381C"}[revision]
|
||||
io = {"7.2": _io_v7_2}[revision]
|
||||
connectors = {"7.2": _connectors_v7_2}[revision]
|
||||
|
||||
LatticePlatform.__init__(self, device, io, connectors=connectors, toolchain=toolchain)
|
||||
|
||||
def create_programmer(self):
|
||||
return EcpDapProgrammer()
|
||||
|
||||
def do_finalize(self, fragment):
|
||||
LatticePlatform.do_finalize(self, fragment)
|
||||
self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
|
||||
self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
|
||||
self.add_period_constraint(self.lookup_request("eth_clocks:rx", 1, loose=True), 1e9/125e6)
|
||||
28
gateware/sampler.py
Normal file
28
gateware/sampler.py
Normal file
@ -0,0 +1,28 @@
|
||||
from migen import *
|
||||
|
||||
from litex.soc.interconnect.wishbone import *
|
||||
from litex.soc.integration.soc import SoCRegion
|
||||
|
||||
class Sampler(Module):
|
||||
def __init__(self, adc_pins):
|
||||
# TODO correct addr width
|
||||
self.bus = Interface(data_width=32, adr_width=11)
|
||||
|
||||
# self.clock_domains.foo = ClockDomain() is how to add a new clock domain, accessible at self.foo
|
||||
|
||||
# Provide a slow clock to the ADC, 60MHz / 600 = 100kHz
|
||||
self._counter = Signal(32)
|
||||
self.sync += self._counter.eq(self._counter + 1)
|
||||
self.sync += If(self._counter >= 600, self._counter.eq(0), adc_pins.refclk.eq(~adc_pins.refclk))
|
||||
|
||||
# Set config pins to constant values
|
||||
self.comb += adc_pins.oen_b.eq(0) # Data pins enable
|
||||
self.comb += adc_pins.standby.eq(0) # Sampling standby
|
||||
self.comb += adc_pins.dfs.eq(0) # DFS (raw or two's complement)
|
||||
# The only remaining pin, OTR, is an out of range status indicator
|
||||
|
||||
# Read directly from the data pins into the wishbone bus for now, just for bringup
|
||||
self.comb += self.bus.dat_r.eq(adc_pins.data)
|
||||
self.sync += self.bus.ack.eq(0)
|
||||
self.sync += If(self.bus.cyc & self.bus.stb, self.bus.ack.eq(1))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user