fw: i2c progress, writing works (???)
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@ -2,8 +2,7 @@
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//!
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//!
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//! See `gateware/i2c.py` for register information
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//! See `gateware/i2c.py` for register information
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use crate::timer::busy_wait_us;
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use crate::{read_reg, write_reg, timer::busy_wait_us};
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use crate::{read_reg, write_reg};
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use core::arch::asm;
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use core::arch::asm;
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use embedded_hal::blocking::i2c::{Operation, Read, SevenBitAddress, Transactional, Write};
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use embedded_hal::blocking::i2c::{Operation, Read, SevenBitAddress, Transactional, Write};
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@ -33,25 +32,39 @@ use core::fmt::Write as _;
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impl LitexI2c {
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impl LitexI2c {
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pub fn new(base_addr: u32) -> Self {
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pub fn new(base_addr: u32) -> Self {
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LitexI2c { base_addr }
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let mut device = LitexI2c { base_addr };
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device.set_scl(true);
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device.set_sda(true);
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device.set_oe(true);
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device
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}
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}
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fn set_scl(&mut self, val: u32) {
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fn set_reg(&mut self, offset: u32, set: bool) {
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static mut reg_state: u32 = 0;
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unsafe {
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unsafe {
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write_reg(self.base_addr + REG_W, (val & 0x01) << FIELD_W_SCL);
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if set {
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reg_state |= (1 << offset);
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} else {
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reg_state &= !(1 << offset);
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}
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write_reg(self.base_addr + REG_W, reg_state);
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}
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}
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}
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}
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fn set_sda(&mut self, val: u32) {
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fn set_scl(&mut self, set: bool) {
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unsafe {
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defmt::debug!("set scl {}", set);
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write_reg(self.base_addr + REG_W, (val & 0x01) << FIELD_W_SDA);
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self.set_reg(FIELD_W_SCL, set);
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}
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}
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}
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fn set_oe(&mut self, val: u32) {
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fn set_sda(&mut self, set: bool) {
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unsafe {
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self.set_reg(FIELD_W_SDA, set);
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write_reg(self.base_addr + REG_W, (val & 0x01) << FIELD_W_OE);
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}
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}
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fn set_oe(&mut self, set: bool) {
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self.set_reg(FIELD_W_OE, set);
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}
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}
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fn get_sda(&mut self) -> u8 {
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fn get_sda(&mut self) -> u8 {
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@ -63,12 +76,11 @@ impl LitexI2c {
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///
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///
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/// Assumes SCL and SDA have been high due to bus inactivity
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/// Assumes SCL and SDA have been high due to bus inactivity
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unsafe fn start(&mut self) {
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unsafe fn start(&mut self) {
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self.set_oe(1);
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self.set_scl(true);
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self.set_scl(1);
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self.set_sda(true);
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self.set_sda(1);
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busy_wait_us(WAIT_PERIOD_US);
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busy_wait_us(WAIT_PERIOD_US);
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self.set_sda(0);
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self.set_sda(false);
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busy_wait_us(WAIT_PERIOD_US);
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busy_wait_us(WAIT_PERIOD_US);
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}
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}
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@ -76,16 +88,15 @@ impl LitexI2c {
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///
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///
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/// Assumes it was called after an ACK bit
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/// Assumes it was called after an ACK bit
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unsafe fn repeated_start(&mut self) {
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unsafe fn repeated_start(&mut self) {
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self.set_scl(0);
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self.set_scl(false);
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self.set_sda(1);
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self.set_sda(true);
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self.set_oe(1);
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busy_wait_us(WAIT_PERIOD_US);
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busy_wait_us(WAIT_PERIOD_US);
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self.set_scl(1);
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self.set_scl(true);
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busy_wait_us(WAIT_PERIOD_US);
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busy_wait_us(WAIT_PERIOD_US);
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// TODO does this third half-clock break timing?
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// TODO does this third half-clock break timing?
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self.set_sda(0);
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self.set_sda(false);
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busy_wait_us(WAIT_PERIOD_US);
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busy_wait_us(WAIT_PERIOD_US);
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}
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}
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@ -93,49 +104,44 @@ impl LitexI2c {
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///
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///
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/// Assumes it was called after an ACK bit
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/// Assumes it was called after an ACK bit
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unsafe fn stop(&mut self) {
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unsafe fn stop(&mut self) {
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self.set_scl(0);
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self.set_scl(false);
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self.set_sda(0);
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self.set_sda(false);
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self.set_oe(1);
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busy_wait_us(WAIT_PERIOD_US);
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busy_wait_us(WAIT_PERIOD_US);
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self.set_scl(1);
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self.set_scl(true);
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busy_wait_us(WAIT_PERIOD_US);
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busy_wait_us(WAIT_PERIOD_US);
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// TODO does this third half-clock break timing?
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// TODO does this third half-clock break timing?
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//self.set_oe(0); // Disable and let pullup take bus high
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//self.set_oe(false); // Disable and let pullup take bus high
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self.set_sda(1);
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self.set_sda(true);
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busy_wait_us(WAIT_PERIOD_US);
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busy_wait_us(WAIT_PERIOD_US);
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}
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}
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unsafe fn write_byte(&mut self, byte: u8) {
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unsafe fn write_byte(&mut self, byte: u8) {
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self.set_oe(1); // Take SDA to write data out
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for i in 0..8 {
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for i in 0..8 {
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// Write data out before we clock high
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// Write data out before we clock high
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self.set_scl(0);
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self.set_scl(false);
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busy_wait_us(WAIT_PERIOD_US);
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busy_wait_us(WAIT_PERIOD_US);
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// Clock data in
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// Clock data in
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self.set_scl(1);
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self.set_sda((byte >> (7 - i)) & 0x01 != 0);
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self.set_sda(byte as u32 >> (7 - i));
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self.set_scl(true);
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busy_wait_us(WAIT_PERIOD_US)
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busy_wait_us(WAIT_PERIOD_US)
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}
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}
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}
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}
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unsafe fn read_byte(&mut self) -> u8 {
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unsafe fn read_byte(&mut self) -> u8 {
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self.set_oe(0); // De-assert to read data
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let mut out = 0;
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let mut out = 0;
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for i in 0..8 {
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for i in 0..8 {
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self.set_scl(0);
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self.set_scl(false);
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busy_wait_us(WAIT_PERIOD_US);
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busy_wait_us(WAIT_PERIOD_US);
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self.set_scl(1);
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self.set_scl(true);
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busy_wait_us(WAIT_PERIOD_US);
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busy_wait_us(WAIT_PERIOD_US);
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// TODO sampling at the end of the clock may not work 100% of the time
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// TODO sampling at the end of the clock may not work 100% of the time
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// ideally should sample in the middle
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// ideally should sample in the middle
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out |= (self.get_sda() << 7 - i);
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out |= (self.get_sda() << (7 - i));
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}
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}
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out
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out
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@ -143,24 +149,22 @@ impl LitexI2c {
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// Returns if there was an ACK
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// Returns if there was an ACK
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unsafe fn get_ack(&mut self) -> bool {
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unsafe fn get_ack(&mut self) -> bool {
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self.set_oe(0); // Release SDA to read ACK
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self.set_scl(false);
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self.set_sda(1);
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self.set_sda(true);
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self.set_scl(0);
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busy_wait_us(WAIT_PERIOD_US);
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busy_wait_us(WAIT_PERIOD_US);
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self.set_scl(1);
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self.set_scl(true);
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busy_wait_us(WAIT_PERIOD_US);
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busy_wait_us(WAIT_PERIOD_US);
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self.get_sda() == 0
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self.get_sda() == 0
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}
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}
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unsafe fn set_ack(&mut self, ack: bool) {
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unsafe fn set_ack(&mut self, ack: bool) {
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self.set_oe(1); // Take SDA
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self.set_scl(false);
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self.set_sda(!ack as u32);
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self.set_scl(0);
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busy_wait_us(WAIT_PERIOD_US);
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busy_wait_us(WAIT_PERIOD_US);
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self.set_scl(1);
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self.set_sda(!ack);
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self.set_scl(true);
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busy_wait_us(WAIT_PERIOD_US);
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busy_wait_us(WAIT_PERIOD_US);
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}
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}
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}
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}
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@ -176,13 +180,16 @@ impl Write<SevenBitAddress> for LitexI2c {
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// Write address and write bit
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// Write address and write bit
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self.write_byte((address << 1) | 0);
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self.write_byte((address << 1) | 0);
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if !self.get_ack() {
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if !self.get_ack() {
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defmt::debug!("write addr fail");
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self.stop();
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self.stop();
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return Err(Error::Nack);
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return Err(Error::Nack);
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}
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}
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for b in bytes {
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for b in bytes {
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self.write_byte(*b);
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self.write_byte(*b);
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defmt::debug!("write data ");
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if !self.get_ack() {
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if !self.get_ack() {
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defmt::debug!("write data fail");
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self.stop();
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self.stop();
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return Err(Error::Nack);
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return Err(Error::Nack);
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}
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}
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@ -139,7 +139,8 @@ fn main() -> ! {
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match dac.write_config(
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match dac.write_config(
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&mut i2c,
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&mut i2c,
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mcp4726::Config {
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mcp4726::Config {
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vref_source: mcp4726::VRef::UnbufferedVRef,
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//vref_source: mcp4726::VRef::UnbufferedVRef,
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vref_source: mcp4726::VRef::UnbufferedVDD,
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operation: mcp4726::PowerDown::NormalOperation,
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operation: mcp4726::PowerDown::NormalOperation,
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use_2x_gain: false,
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use_2x_gain: false,
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},
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},
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@ -148,20 +149,22 @@ fn main() -> ! {
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Err(_) => defmt::debug!("Write config failed"),
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Err(_) => defmt::debug!("Write config failed"),
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}
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}
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//match dac.read_status(&mut i2c) {
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match dac.read_status(&mut i2c) {
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// Ok(status) => {
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Ok(status) => {
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// defmt::debug!(
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defmt::debug!(
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// "DAC status: ready: {}, powered: {}",
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"DAC status: ready: {}, powered: {}",
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// status.ready,
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status.ready,
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// status.device_powered
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status.device_powered
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// );
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);
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// if sock.can_send() {
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if sock.can_send() {
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// write!(sock, "DAC: ready: {}, powered: {}", status.ready, status.device_powered);
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write!(sock, "DAC: ready: {}, powered: {}", status.ready, status.device_powered);
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// }
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}
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// }
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}
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// Err(_) => defmt::debug!("Error reading from DAC"),
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Err(_) => defmt::debug!("Error reading from DAC"),
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//};
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};
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dac.write_dac(&mut i2c, 800);
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//if toggle {
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//if toggle {
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// sampler::clear_buffers();
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// sampler::clear_buffers();
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