From c887cd135c6b746aa26a50b774ec3f3972fc8e71 Mon Sep 17 00:00:00 2001 From: David Lenfesty Date: Sun, 7 May 2023 10:54:09 -0600 Subject: [PATCH] hw: update README for new revision --- hardware/colorlight-base/README.md | 54 +++++++++++++++++++++++------- 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/hardware/colorlight-base/README.md b/hardware/colorlight-base/README.md index 43d0a99..c67922d 100644 --- a/hardware/colorlight-base/README.md +++ b/hardware/colorlight-base/README.md @@ -1,3 +1,22 @@ +# Building this board + +BOM can be generated using KiBOM (configuration is tracked in git, so you just need to use it). +The version on PyPI may be out of date, so either install manually or with the following git command: + +```shell +pip install git+https://github.com/SchrodingersGAT/KiBoM +``` + +Then you can create new generator, using the following CLI: + +``` +"/usr/bin/python3" "-m" "kibom" "%I" "%O" +``` + +The "prototype" variant can be specified, and that will remove the ADCs from the BOM. + +For manufacturing, use the most recent ZIP file of gerbers in the `gerbers/` folder. + # Manufacturing specs Designed for JLC7628 stackup. @@ -6,15 +25,26 @@ Designed for JLC7628 stackup. ## Revision A -- Missing silkscreen labels for debug headers and UART headers -- Pogo pins not *quite* centered. -- Pogo pins should export 4 parts, not 1. -- Power regulator and ADC should be moved to underside of board to avoid potential mechanical conflicts. -- Ethernet magnetics footprint is incorrect (too slim). -- Should have some way to provide power for standalone debugging (USB?) -- I2C should have DNP pullup resistor footprints -- Reset and/or power button would be nice -- Pads on DDR connector could be thinned slightly -- VREF is floating on ADCs -- led is on same FPGA pin as ADC1 refclk (U16) -- Need to figure out the pin length for mounting the board directly to preprocessor +Initial revision, used for prototype and initial bringup. + +### Issues being addressed +- [X] Missing silkscreen labels for debug headers and UART headers +- [X] Pogo pins should export 4 parts, not 1. +- [X] Power regulator and ADC should be moved to underside of board to avoid potential mechanical conflicts. +- [X] Ethernet magnetics footprint is incorrect (too slim). +- [X] I2C should have DNP pullup resistor footprints +- [X] Pads on DDR connector could be thinned slightly +- [X] led is on same FPGA pin as ADC1 refclk (U16) +- [X] Need to figure out the pin length for mounting the board directly to preprocessor + +### Issues not being addressed + +- [ ] Should have some way to provide power for standalone debugging (not doing) +- [ ] Reset and/or power button would be nice (not doing) +- [ ] Pogo pins not *quite* centered. +- [ ] ~~VREF is floating on ADCs~~ + +## Revision B + +Intended to be the final revision. Fixes all known major issues with revision A, +improves silkscreen and BOM generation.