From cf1c1290546c2ef8c3c38090287bb90cca78e26a Mon Sep 17 00:00:00 2001
From: David Lenfesty <lenfesty@ualberta.ca>
Date: Sun, 22 Jan 2023 20:25:39 -0700
Subject: [PATCH] gateware: name submodules properly and start fleshing out CLI

---
 gateware/soc.py | 41 +++++++++++++++++++++++++++--------------
 1 file changed, 27 insertions(+), 14 deletions(-)

diff --git a/gateware/soc.py b/gateware/soc.py
index 88ead03..9933955 100644
--- a/gateware/soc.py
+++ b/gateware/soc.py
@@ -6,10 +6,11 @@ from amaranth_boards import colorlight_i9
 from amaranth_soc.wishbone import Interface, Arbiter, Decoder
 from amaranth_soc.memory import MemoryMap
 
-from typing import List
-
 from minerva.core import Minerva
 
+from typing import List
+from argparse import ArgumentParser
+
 class Blinky(Elaboratable):
     def __init__(self):
         self.count = Signal(64)
@@ -157,6 +158,7 @@ class LEDPeripheral(Elaboratable, Interface):
         return m
 
 
+# TODO clean this up, generate binary here, maybe even run cargo build
 def load_firmware_for_mem() -> List[int]:
     with open('../firmware/fw.bin', 'rb') as f:
         # Stored as little endian, LSB first??
@@ -178,9 +180,9 @@ class Core(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules += self.cpu
-        m.submodules += self.arbiter
-        m.submodules += self.decoder
+        m.submodules.cpu = self.cpu
+        m.submodules.arbiter = self.arbiter
+        m.submodules.decoder = self.decoder
 
         # Connect ibus and dbus together for simplicity for now
         minerva_wb_features = ["cti", "bte", "err"]
@@ -210,24 +212,22 @@ class Core(Elaboratable):
 
 
         fw = load_firmware_for_mem()
-        print(len(fw))
-        print(fw)
 
         # Hook up memory space
         self.rom = ROM(fw)
-        m.submodules += self.rom
+        m.submodules.rom = self.rom
         # Problem: not sure to handle how we do byte vs word addressing properly
         # So doing this shift is a bit of a hacky way to impl anything
         start, _stop, _step = self.decoder.add(self.rom, addr=(0x01000000 >> 2))
         print(f"ROM added at 0x{start:08x}")
 
         self.ram = RAM()
-        m.submodules += self.ram
+        m.submodules.ram = self.ram
         start, _stop, _step = self.decoder.add(self.ram)
         print(f"RAM added at 0x{start:08x}")
 
         self.led = LEDPeripheral(self.led_signal)
-        m.submodules += self.led
+        m.submodules.led = self.led
         start, _stop, _step = self.decoder.add(self.led)
         print(f"LED added at 0x{start:08x}")
 
@@ -251,11 +251,12 @@ class SoC(Elaboratable):
 
         led_signal = platform.request("led")
         core = Core(led_signal)
-        m.submodules += core
+        m.submodules.core = core
 
         return m
 
 
+# TODO add more harnessing
 class TestDevice(Elaboratable):
     def __init__(self):
         pass
@@ -265,10 +266,11 @@ class TestDevice(Elaboratable):
         m = Module()
         led_signal = Signal()
         core = Core(led_signal)
-        m.submodules += core
+        m.submodules.core = core
 
         return m
 
+# TODO add structure to add regression tests
 def run_sim():
     dut = TestDevice()
     sim = Simulator(dut)
@@ -285,6 +287,17 @@ def run_sim():
 
 
 if __name__ == "__main__":
-    colorlight_i9.Colorlight_i9_Platform().build(SoC(), debug_verilog=True)
+    args = ArgumentParser(description="ARVP Sonar Acquisition FPGA gateware.")
+    args.add_argument("--build", action="store_true", help="Build bitstream.")
+    args.add_argument("--gen-debug-verilog", action="store_true", help="Save debug verilog.")
+    # TODO maybe allow an optional arg to specify an individual test to run?
+    args.add_argument("--test", action="store_true", help="Run RTL test suite and report results.")
+    args.add_argument("--save-vcd", action="store_true", help="Save VCD waveforms from test(s).")
+    args = args.parse_args()
 
-    #run_sim()
\ No newline at end of file
+    if args.build:
+        colorlight_i9.Colorlight_i9_Platform().build(SoC(), debug_verilog=args.gen_debug_verilog)
+
+    if args.test:
+        # TODO pass save_vcd arg through
+        run_sim()