gw: start writing circular buffer
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@ -1,7 +1,113 @@
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from migen import *
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from litex.soc.interconnect.wishbone import *
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from litex.soc.integration.soc import SoCRegion
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from math import log2, ceil
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"""
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Random implementation notes:
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- Circular buffers can keep overwriting. We only need a setting to say how many samples to save after
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trigger occurs.
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- Data valid from samplers to FIFOs can simply be gated via the enable signal. Everything can just run
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all the time to keep things simple
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- can we correct clock skew on the sample clock via Lattice primitives? I think it's possible. I doubt it
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matters. Would need significant calibration effort to even have it be accurate.
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"""
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class CircularBuffer(Module):
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"""
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Circular buffer implementation that allows users to read the entire data.
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Assumptions:
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- Reading values while writes are ocurring does not need to have well-defined behaviour
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Implementation is largely based on Migen SyncFIFO, just tweaked to operate how I want
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"""
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def __init__(self, width: int, depth: int) -> None:
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storage = Memory(width=width, depth=depth)
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self.specials += storage
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ptr_width = ceil(log2(depth))
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# External Signals
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self.len = Signal(ptr_width) # Amount of valid data in the buffer
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self.clear = Signal() # Strobe to clear memory
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self.rd_addr = Signal(ptr_width)
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self.rd_data = Signal(width)
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self.wr_data = Signal(width)
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self.wr_ready = Signal() # Output, signals buffer is ready to be written to
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self.wr_valid = Signal() # Input, high when data is present to be written
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wr_ptr = Signal(ptr_width)
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rd_ptr = Signal(ptr_width)
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empty = Signal(reset=1) # Extra signal to distinguish between full and empty condition
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# Hook write input signals to memory
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wr_port = storage.get_port(write_capable=True)
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# Always ready to write data into memory, so hook these signals straight in
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self.comb += [
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wr_port.adr.eq(wr_ptr),
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wr_port.dat_w.eq(self.wr_data),
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wr_port.we.eq(self.wr_valid),
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self.wr_ready.eq(1), # We are always ready to write data in
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]
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# Advance write (and potentially read)
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self.sync += [
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If(self.wr_valid,
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# We aren't empty anymore, and we won't be until we are cleared
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empty.eq(0),
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# Advance write pointer
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If(wr_ptr < depth,
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wr_ptr.eq(wr_ptr + 1))
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.Else(wr_ptr.eq(0)),
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# Advance read pointer if we are full (e.g. overwrite old data)
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If(~empty & wr_ptr == rd_ptr,
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If(rd_ptr < depth,
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rd_ptr.eq(rd_ptr + 1))
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.Else(rd_ptr.eq(0))
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)
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)
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]
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# TODO should I actually set async_read?
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rd_port = storage.get_port(async_read=True)
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# Set read addr so 0 starts at rd_ptr and wraps around, and connect read data up
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self.comb += [
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If(self.rd_addr + rd_ptr < depth,
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rd_port.adr.eq(self.rd_addr + rd_ptr))
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.Else(
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rd_port.adr.eq(self.rd_addr - (depth - rd_ptr))
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),
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self.rd_data.eq(rd_port.dat_r),
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]
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# Export the length present
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self.comb += [
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If(empty, self.len.eq(0))
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.Else(
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If(wr_ptr >= rd_ptr,
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self.len.eq(wr_ptr - rd_ptr))
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.Elif(wr_ptr != rd_ptr,
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self.len.eq(depth - (rd_ptr - wr_ptr)))
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.Else(
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self.len.eq(depth)
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)
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),
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]
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# "Clear" out memory if clear is strobed
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# NOTE really clear should be hooked into reset, but I'm not clear on how to do that.
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# Technically there's some glitches that can happen here if we write data while clear
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# is asserted, but that shouldn't happen and it's fine if it does tbh.
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self.sync += If(self.clear,
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wr_ptr.eq(0), rd_ptr.eq(0), empty.eq(0))
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class Sampler(Module):
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def __init__(self, adc_pins):
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@ -26,3 +132,63 @@ class Sampler(Module):
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self.sync += self.bus.ack.eq(0)
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self.sync += If(self.bus.cyc & self.bus.stb, self.bus.ack.eq(1))
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def fifo_testbench():
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dut = CircularBuffer(9, 24)
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def test_fn():
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assert (yield dut.len) == 0
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assert (yield dut.wr_ready) == 1
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# Clock some data in, check len
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data = [0xDE, 0xAD, 0xBE, 0xEF]
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for b in data:
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(yield dut.wr_data.eq(b))
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(yield dut.wr_valid.eq(1))
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yield
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fifo_len = (yield dut.len)
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assert fifo_len == 4, f"len should be 4, is {fifo_len}"
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# Stop clocking data in
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(yield dut.wr_valid.eq(0))
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# Reset
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(yield dut.clear.eq(1))
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yield
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(yield dut.cleart.eq(0))
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# Len should be cleared
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assert (yield dut.len) == 0
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# Clock more data in than capacity, check that we can read out
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# the expected data
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data = [r for r in range(32)] # Yes yes I could use a generator but I want to slice it later
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for b in data:
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(yield dut.wr_data.eq(b))
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(yield dut.wr_valid.eq(1))
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yield
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data_len = (yield dut.len)
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assert data_len == 24
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out_data = []
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for i in range(24):
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(yield dut.rd_addr.eq(i))
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out_data.append((yield dut.rd_data))
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assert out_data[i] == data[i + 8], f"Data mismatch at index {i}"
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# At this point, seems to be working
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run_simulation(dut, test_fn())
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if __name__ == "__main__":
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import argparse
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args = argparse.ArgumentParser()
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args.add_argument("--fifo", action="store_true", help="Run FIFO tests")
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args = args.parse_args()
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if args.fifo:
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fifo_testbench()
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