diff --git a/gateware/sampler/circular_buffer.py b/gateware/sampler/circular_buffer.py
index d1b5f1f..513e07b 100644
--- a/gateware/sampler/circular_buffer.py
+++ b/gateware/sampler/circular_buffer.py
@@ -21,7 +21,7 @@ class CircularBuffer(Module):
         ptr_width = ceil(log2(depth))
 
         # External Signals
-        self.len = Signal(ptr_width) # Amount of valid data in the buffer
+        self.len = Signal(ptr_width + 1) # Amount of valid data in the buffer
         self.clear = Signal()                # Strobe to clear memory
         self.rd_addr = Signal(ptr_width)
         self.rd_data = Signal(width)
diff --git a/gateware/sampler/controller.py b/gateware/sampler/controller.py
index 1144c4d..5878399 100644
--- a/gateware/sampler/controller.py
+++ b/gateware/sampler/controller.py
@@ -31,7 +31,7 @@ class SamplerController(Module):
         Bit 0 - Begin capture. Resets all FIFOs and starts the peak detector
 
     0x01: Status Register (RO)
-        Bit 0 - Capture complete. Set by peak detection block and cleared by software or when 
+        Bit 0 - Capture complete. Set by peak detection block and cleared when capture is began
 
     0x02: trigger_run_len (RW)
         Number of samples to acquire after triggering sample.
@@ -67,6 +67,9 @@ class SamplerController(Module):
 
         # Connect each buffer to each sampler
         for buffer, sampler in zip(self.buffers, self.samplers):
+            self.submodules += buffer
+            self.submodules += sampler
+
             self.comb += [
                 # Connect only top 9 bits to memory
                 buffer.wr_data.eq(sampler.data[1:]),
@@ -76,8 +79,9 @@ class SamplerController(Module):
 
 
         # Each sampler gets some chunk of memory at least large enough to fit
-        # all of it's data, so use that as a consistent offset
-        sample_mem_addr_width = ceil(log2(buffer_len))
+        # all of it's data, so use that as a consistent offset. Use a minimum
+        # address of 0x800 to avoid conflicts with control registers
+        sample_mem_addr_width = max(ceil(log2(buffer_len)), ceil(log2(0x800)))
         # 1 control block + number of channels used = control bits
         control_block_addr_width = ceil(log2(num_channels + 1))
 
@@ -100,11 +104,9 @@ class SamplerController(Module):
             adr = (i + 1) << sample_mem_addr_width
             print(f"Sampler {i} available at 0x{adr:08x}")
 
-        self.decoder = Decoder(self.bus, slaves)
-        # TODO how to submodule
-        self.submodules.decoder = self.decoder
+        self.submodules.decoder = Decoder(self.bus, slaves)
 
-        self.peak_detector = PeakDetector(10)
+        self.submodules.peak_detector = PeakDetector(10)
         self.comb += [
             # Simply enable whenever we start capturing
             self.peak_detector.enable.eq(sample_enable),