fw: write common read/write function

firmware/Cargo.lock

@@ -37,6 +37,7 @@ dependencies = [
 name = "fw"
 version = "0.1.0"
 dependencies = [
+ "embedded-hal",
  "panic-halt",
  "riscv-rt",
 ]

firmware/Cargo.toml

@@ -8,3 +8,4 @@ edition = "2021"
 [dependencies]
 riscv-rt = "0.11.0"
 panic-halt = "0.2.0"
+embedded-hal = "0.2.7"

firmware/src/eth.rs

@@ -13,35 +13,23 @@ const ETHMAC_SRAM_READER_LENGTH: u32 = LITEETH_BASE + 0x828;
 const ETHMAC_SRAM_READER_START: u32 = LITEETH_BASE + 0x818;
 const ETHMAC_SRAM_READER_READY: u32 = LITEETH_BASE + 0x81c;
 
-fn write_u32_reg(addr: u32, value: u32) {
+use crate::{write_reg, read_reg};
-    use core::ptr::write;
-    unsafe {
-        write(addr as *mut u32, value);
-    }
-}
 
-fn read_u32_reg(addr: u32) -> u32 {
+pub unsafe fn is_wishbone_correct() -> bool {
-    use core::ptr::read;
+    let value: u32 = read_reg(LITEETH_BASE + 4);
-    unsafe {
-        return read(addr as *mut u32);
-    }
-}
-
-pub fn is_wishbone_correct() -> bool {
-    let value = read_u32_reg(LITEETH_BASE + 4);
 
     // If this isn't true, we screwed.
     return value == 0x12345678;
 }
 
-pub fn init() {
+pub unsafe fn init() {
     // Clear any potential pending events
-    write_u32_reg(ETHMAC_SRAM_WRITER_EV_PENDING, 1);
+    write_reg(ETHMAC_SRAM_WRITER_EV_PENDING, 1u32);
-    write_u32_reg(ETHMAC_SRAM_READER_EV_PENDING, 1);
+    write_reg(ETHMAC_SRAM_READER_EV_PENDING, 1u32);
 
     // Disable all events
-    write_u32_reg(ETHMAC_SRAM_WRITER_EV_ENABLE, 0);
+    write_reg(ETHMAC_SRAM_WRITER_EV_ENABLE, 0u32);
-    write_u32_reg(ETHMAC_SRAM_READER_EV_ENABLE, 0);
+    write_reg(ETHMAC_SRAM_READER_EV_ENABLE, 0u32);
 }
 
 // a8:a1:59:32:a7:a5
@@ -49,7 +37,7 @@ const ares_mac: [u8; 6] = [0xA8, 0xA1, 0x59, 0x32, 0xA7, 0xA5];
 const fake_mac: [u8; 6] = [0x00, 0x01, 0x02, 0x03, 0x04, 0x05];
 
 /// Just make an ethernet frame and yeet it
-pub fn tranmsit() {
+pub unsafe fn tranmsit() {
     // Preamble/start delimiter/crc are all handled for us by the MAC
     let frame: [u8; 18] = [
         // TODO endianness of MAC addresses?
@@ -71,14 +59,12 @@ pub fn tranmsit() {
     tx_slot[..18].copy_from_slice(&frame);
 
     // Set slot and packet length
-    write_u32_reg(ETHMAC_SRAM_READER_SLOT, 0);
+    write_reg(ETHMAC_SRAM_READER_SLOT, 0u32);
-    write_u32_reg(ETHMAC_SRAM_READER_LENGTH, 18);
+    write_reg(ETHMAC_SRAM_READER_LENGTH, 18u32);
 
     // Wait to be ready
-    while read_u32_reg(ETHMAC_SRAM_READER_READY) == 0 {}
+    while read_reg::<u32>(ETHMAC_SRAM_READER_READY) == 0 {}
 
     // Write!
-    write_u32_reg(ETHMAC_SRAM_READER_START, 1);
+    write_reg(ETHMAC_SRAM_READER_START, 1u32);
-    
-
 }

firmware/src/main.rs

@@ -3,7 +3,7 @@
 
 extern crate panic_halt;
 
-use core::{arch::asm, ptr::write};
+use core::{arch::asm, ptr::{write, read}};
 
 use riscv_rt::entry;
 
@@ -21,15 +21,12 @@ fn main() -> ! {
         500_000
     };
 
-    // do something here
     loop {
-        unsafe {
+        //eth::tranmsit();
-            //eth::tranmsit();
+        write_led(0);
-            write_led(0);
+        busy_wait(blink_period);
-            busy_wait(blink_period);
+        write_led(1);
-            write_led(1);
+        busy_wait(blink_period);
-            busy_wait(blink_period);
-        }
     }
 }
 
@@ -42,7 +39,13 @@ fn busy_wait(num_nops: u32) {
 }
 
 fn write_led(val: u32) {
-    unsafe {
+    unsafe { write_reg(0x0100200, val); }
-        write(0x01002000 as *mut u32, val);
+}
-    }
+
+unsafe fn write_reg<T>(addr: u32, value: T) {
+    write(addr as *mut T, value);
+}
+
+unsafe fn read_reg<T>(addr: u32) -> T {
+    return read(addr as *mut T);
 }