gateware: Properly migrate I2C test into my new framework
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156
gateware/i2c.py
156
gateware/i2c.py
@ -121,159 +121,3 @@ class I2C(Elaboratable):
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return m
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from amaranth.lib.io import pin_layout
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i2c_layout = [
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("sda", pin_layout(1, "io")),
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("scl", pin_layout(1, "io")),
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]
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class I2CBusSimulator(Elaboratable):
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def __init__(self):
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self.interfaces = []
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self.sda = Signal()
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self.scl = Signal()
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def elaborate(self, target):
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assert target is None, "This bus simulator should never be used in real hardware!"
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n = len(self.interfaces)
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m = Module()
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m.d.comb += self.sda.eq(1)
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m.d.comb += self.scl.eq(1)
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# TODO maybe output a bus contention signal?
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# First interfaces get priority over interfaces added after
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for i in reversed(range(n)):
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# Emulate bus drivers
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with m.If(self.interfaces[i].sda.oe):
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m.d.comb += self.sda.eq(self.interfaces[i].sda.o)
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with m.If(self.interfaces[i].scl.oe):
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m.d.comb += self.scl.eq(self.interfaces[i].scl.o)
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pass
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# Connect inputs to bus value
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m.d.comb += [
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self.interfaces[i].sda.i.eq(self.sda),
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self.interfaces[i].scl.i.eq(self.scl),
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]
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return m
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def create_interface(self) -> Record:
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new_interface = Record(i2c_layout)
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self.interfaces.append(new_interface)
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return new_interface
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class TestHarness(Elaboratable):
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def __init__(self):
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self.i2c = I2CBusSimulator()
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self.uut = I2C(10_000_000, 100_000, self.i2c.create_interface())
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self.i2c_target = I2CTarget(self.i2c.create_interface())
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def elaborate(self, platform):
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assert platform is None
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m = Module()
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m.submodules.i2c = self.i2c
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m.submodules.uut = self.uut
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m.submodules.i2c_target = self.i2c_target
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m.d.comb += self.i2c_target.address.eq(0xAA >> 1)
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return m
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import unittest
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import os
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import sys
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import inspect
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from contextlib import nullcontext
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from typing import Generator
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from tests import BaseTestClass, provide_testcase_name
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class TestCSROperation(BaseTestClass):
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def setUp(self):
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self.harness = TestHarness()
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@provide_testcase_name
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def test_send_byte(self, test_name):
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def test():
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yield Tick()
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self._run_test(test, test_name)
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# TODO switch to unittest or something
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if __name__ == "__main__":
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unittest.main()
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def write_csr(bus, index, data):
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yield bus.addr.eq(index)
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yield bus.w_stb.eq(1)
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yield bus.w_data.eq(data)
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yield Tick()
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yield bus.w_stb.eq(0)
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yield Tick()
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def read_csr(bus, index):
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yield bus.r_strb.eq(1)
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ret = yield bus.r_data
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yield Tick()
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yield bus.r_stb.eq(0)
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yield Tick()
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harness = TestHarness()
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sim = Simulator(harness)
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def test_proc():
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#send start
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yield from write_csr(harness.uut.bus, 0, 1)
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# TODO shouldn't need to do this, if I did a proper CSR read maybe?
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yield Tick()
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yield Tick()
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# TODO I want something like read_csr, unsure how to implement
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# Wait for
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while True:
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busy = yield harness.uut._initiator.busy
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if not busy:
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break
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else:
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yield Tick()
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# Set data
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yield from write_csr(harness.uut.bus, 2, 0xAA)
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# Write data
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yield from write_csr(harness.uut.bus, 0, 1 << 2)
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did_start = False
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for i in range(1000):
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start_cond = yield harness.i2c_target.start
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yield Tick()
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if start_cond:
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did_start = True
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break
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#assert did_start, "Idnaoidnwaioudnwaoiun"
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print(did_start)
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sim.add_clock(100e-9)
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sim.add_sync_process(test_proc)
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with sim.write_vcd('test.vcd'):
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sim.reset()
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sim.run()
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@ -14,6 +14,9 @@ class TestHarness(Elaboratable):
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self.uut = I2C(10_000_000, 100_000, self.i2c.create_interface())
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self.i2c_target = I2CTarget(self.i2c.create_interface())
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self.start_latch = Signal()
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self.clear_start = Signal()
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def elaborate(self, platform):
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assert platform is None
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@ -26,6 +29,12 @@ class TestHarness(Elaboratable):
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m.d.comb += self.i2c_target.address.eq(0xAA >> 1)
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with m.If(self.i2c_target.start):
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m.d.sync += self.start_latch.eq(self.i2c_target.start)
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with m.If(self.clear_start):
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m.d.sync += self.start_latch.eq(0)
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return m
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@ -34,13 +43,58 @@ class TestCSROperation(BaseTestClass):
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self.harness = TestHarness()
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@provide_testcase_name
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def test_send_byte(self, test_name):
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def test():
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def _write_csr(self, bus, index, data):
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yield bus.addr.eq(index)
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yield bus.w_stb.eq(1)
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yield bus.w_data.eq(data)
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yield Tick()
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yield bus.w_stb.eq(0)
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yield Tick()
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def _wait_for_signal(self, signal, polarity=False, require_edge=True, timeout=1000):
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ready_for_edge = not require_edge # If we don't require edge, we can just ignore
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while True:
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timeout -= 1
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if timeout == 0:
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self.fail(f"_wait_for_signal({signal}, {polarity}, {require_edge}, {timeout}, timed out!")
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read = yield signal
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if read == polarity:
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if ready_for_edge:
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break
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else:
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ready_for_edge = True
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yield Tick()
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# NOTE So ideally there are more test cases... but the initiator itself is well tested,
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# and we only really need it to work for a limited set of use cases, so exhaustive testing
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# isn't a huge deal. As well, we can cover all valid uses of the signals with one test.
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@provide_testcase_name
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def test_operation(self, test_name):
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def test():
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#send start
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yield from self._write_csr(self.harness.uut.bus, 0, 1)
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yield from self._wait_for_signal(self.harness.uut._initiator.busy, require_edge=True)
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# Set data
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yield from self._write_csr(self.harness.uut.bus, 2, 0xAA)
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# Write data
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yield from self._write_csr(self.harness.uut.bus, 0, 1 << 2)
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yield from self._wait_for_signal(self.harness.uut._initiator.busy)
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# First byte has been written
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did_start = yield self.harness.start_latch
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self.assertTrue(did_start)
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self._run_test(test, test_name)
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i2c_layout = [
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("sda", pin_layout(1, "io")),
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("scl", pin_layout(1, "io")),
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@ -22,16 +22,19 @@ class BaseTestClass(unittest.TestCase):
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raise NotImplementedError(f"Must define a self.harness module for TestCase {self.__class__.__name__}!")
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sim.add_clock(100e-9)
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sim.add_sync_process(test)
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sim.reset()
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# Pretty hacky way to pass this info in but does it look like I care?
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if os.environ.get("TEST_SAVE_VCD"):
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ctx = sim.write_vcd(f"vcd_out/{name}.vcd")
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ctx = sim.write_vcd(f"vcd_out/{name}.vcd")
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else:
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ctx = nullcontext()
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with ctx:
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sim.add_sync_process(test)
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sim.run()
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del sim
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def provide_testcase_name(fn):
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