gw: get i2c up and running (ish) in simulation
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@ -5,21 +5,30 @@ extern crate panic_halt;
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use core::{arch::asm, ptr::{write, read}};
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use embedded_hal::prelude::_embedded_hal_blocking_i2c_Write;
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use riscv_rt::entry;
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mod eth;
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mod i2c;
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// use `main` as the entry point of this application
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// `main` is not allowed to return
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#[entry]
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fn main() -> ! {
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eth::init();
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//unsafe { eth::init(); }
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let blink_period = if eth::is_wishbone_correct() {
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10_000_000
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} else {
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500_000
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};
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//let blink_period = unsafe {
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// if eth::is_wishbone_correct() {
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// 10_000_000
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// } else {
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// 500_000
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// }
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//};
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let blink_period = 10_000_000u32;
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let mut i2c = i2c::AmlibI2c::new(0x01003000);
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let data = [0u8, 2u8];
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i2c.write(0xAA, &data).unwrap();
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loop {
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//eth::tranmsit();
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@ -63,7 +63,7 @@ class I2C(Elaboratable):
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# Set up CSR bus
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addr_width = ceil(log2(64)) # Support up to 64 registers just because
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data_width = 32 # 32 bit bus
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data_width = 8 # 32 bit bus
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self._csr_mux = Multiplexer(addr_width=addr_width, data_width=data_width)
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# TODO export the addresses of these somehow
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self._csr_mux.add(self.CR)
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@ -4,6 +4,9 @@ from amaranth import *
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from amaranth.sim import *
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from amaranth_boards import colorlight_i9
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from amaranth_soc.wishbone import *
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from amaranth_soc import csr
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from amaranth_soc.csr.wishbone import WishboneCSRBridge
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from amaranth.lib.io import pin_layout
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from minerva.core import Minerva
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@ -38,6 +41,18 @@ def load_firmware_for_mem() -> List[int]:
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return out
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class I2CPads:
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"""Small structure to avoid using record. Unsure what the proper solution is"""
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class Pad:
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def __init__(self):
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self.o = Signal()
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self.i = Signal()
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self.oe = Signal()
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def __init__(self):
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self.scl = self.Pad()
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self.sda = self.Pad()
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class Core(Elaboratable):
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def __init__(self, clk25, led_signal, eth_interface):
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self.count = Signal(64)
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@ -124,12 +139,36 @@ class Core(Elaboratable):
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start, _stop, _step = self.decoder.add(self.led)
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print(f"LED added at 0x{start:08x}")
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m.submodules.uart = uart.UART(10e6)
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# TODO how to set addr_width?
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# Create CSR bus and connect it to Wishbone
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self.csr = csr.Decoder(addr_width=10, data_width=8)
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m.submodules.csr = self.csr
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print(f"CSR bus added at 0x{start:08x}")
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# I2C (connected to DAC for VCO and ADC?)
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Signal()
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if platform is not None:
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i2c_pads = platform.request("i2c")
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else:
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# TODO this is hacky crap
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i2c_pads = I2CPads()
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with m.If(i2c_pads.scl.oe):
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m.d.comb += i2c_pads.scl.i.eq(0)
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with m.Else():
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m.d.comb += i2c_pads.scl.i.eq(1)
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self.i2c = i2c.I2C(50e6, 100e3, i2c_pads)
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m.submodules.i2c = self.i2c
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self.csr.add(self.i2c.bus)
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self.csr_bridge = WishboneCSRBridge(self.csr.bus, data_width=32, name="CSR")
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m.submodules.csr_bridge = self.csr_bridge
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# TODO shouldn't have to hard-specify this address
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start, _stop, _step = self.decoder.add(self.csr_bridge.wb_bus, addr=0x01003000)
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# Ethernet
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self.eth = LiteEth(self.eth_interface)
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m.submodules.eth = self.eth
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start, _stop, _step = self.decoder.add(self.eth, addr=0x02000000)
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#start, _stop, _step = self.decoder.add(self.eth, addr=0x02000000)
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print(f"LiteETH added at 0x{start:08x}")
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# Connect arbiter to decoder
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@ -167,7 +206,7 @@ def run_sim():
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sim = Simulator(dut)
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def proc():
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for i in range(1000):
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for i in range(10000):
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yield Tick()
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sim.add_clock(1e-6)
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@ -205,5 +244,6 @@ if __name__ == "__main__":
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unittest.main(module=mod, argv=[sys.argv[0]])
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if args.sim:
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print("Running simulation...")
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run_sim()
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