From fe379be39b13b9d1110a0faf6e1cb3381ff92193 Mon Sep 17 00:00:00 2001 From: David Lenfesty Date: Sat, 18 Feb 2023 11:56:39 -0700 Subject: [PATCH] gateware: saving some state again --- gateware/docs/sampler_clock_design.md | 40 + gateware/eth.py | 51 +- gateware/gen_liteeth.sh | 2 +- gateware/liteeth/csr.csv | 45 + .../liteeth/doc/_build/doctrees/ctrl.doctree | Bin 0 -> 14349 bytes .../doc/_build/doctrees/environment.pickle | Bin 0 -> 170524 bytes .../doc/_build/doctrees/ethmac.doctree | Bin 0 -> 61485 bytes .../doc/_build/doctrees/ethphy.doctree | Bin 0 -> 24496 bytes .../liteeth/doc/_build/doctrees/index.doctree | Bin 0 -> 5101 bytes .../doc/_build/doctrees/interrupts.doctree | Bin 0 -> 4706 bytes gateware/liteeth/doc/_build/html/.buildinfo | 4 + .../doc/_build/html/_sources/ctrl.rst.txt | 78 + .../doc/_build/html/_sources/ethmac.rst.txt | 380 ++ .../doc/_build/html/_sources/ethphy.rst.txt | 138 + .../doc/_build/html/_sources/index.rst.txt | 31 + .../_build/html/_sources/interrupts.rst.txt | 18 + .../doc/_build/html/_static/WaveDrom.js | 3 + .../doc/_build/html/_static/alabaster.css | 703 +++ .../liteeth/doc/_build/html/_static/basic.css | 903 ++++ .../doc/_build/html/_static/custom.css | 1 + .../doc/_build/html/_static/default.js | 3 + .../doc/_build/html/_static/doctools.js | 156 + .../html/_static/documentation_options.js | 14 + .../liteeth/doc/_build/html/_static/file.png | Bin 0 -> 286 bytes .../doc/_build/html/_static/language_data.js | 199 + .../liteeth/doc/_build/html/_static/minus.png | Bin 0 -> 90 bytes .../liteeth/doc/_build/html/_static/plus.png | Bin 0 -> 90 bytes .../doc/_build/html/_static/pygments.css | 83 + .../doc/_build/html/_static/searchtools.js | 566 +++ .../_build/html/_static/sphinx_highlight.js | 144 + gateware/liteeth/doc/_build/html/ctrl.html | 213 + gateware/liteeth/doc/_build/html/ethmac.html | 567 +++ gateware/liteeth/doc/_build/html/ethphy.html | 320 ++ .../liteeth/doc/_build/html/genindex.html | 109 + gateware/liteeth/doc/_build/html/index.html | 144 + .../liteeth/doc/_build/html/interrupts.html | 128 + gateware/liteeth/doc/_build/html/objects.inv | Bin 0 -> 993 bytes gateware/liteeth/doc/_build/html/search.html | 128 + .../liteeth/doc/_build/html/searchindex.js | 1 + gateware/liteeth/doc/_static/WaveDrom.js | 3 + gateware/liteeth/doc/_static/default.js | 3 + gateware/liteeth/doc/conf.py | 17 + gateware/liteeth/doc/ctrl.rst | 78 + gateware/liteeth/doc/ethmac.rst | 380 ++ gateware/liteeth/doc/ethphy.rst | 138 + gateware/liteeth/doc/index.rst | 31 + gateware/liteeth/doc/interrupts.rst | 18 + .../liteeth/gateware/build_liteeth_core.sh | 5 + gateware/liteeth/gateware/liteeth_core.lpf | 132 + gateware/liteeth/gateware/liteeth_core.v | 3898 +++++++++++++++++ gateware/liteeth/gateware/liteeth_core.ys | 8 + .../liteeth/software/include/generated/csr.h | 409 ++ .../liteeth/software/include/generated/git.h | 8 + .../liteeth/software/include/generated/mem.h | 20 + .../liteeth/software/include/generated/soc.h | 56 + gateware/main.py | 4 + gateware/test.gtwk | 3 + requirements.txt | 2 + 58 files changed, 10381 insertions(+), 4 deletions(-) create mode 100644 gateware/docs/sampler_clock_design.md mode change 100644 => 100755 gateware/gen_liteeth.sh create mode 100644 gateware/liteeth/csr.csv create mode 100644 gateware/liteeth/doc/_build/doctrees/ctrl.doctree create mode 100644 gateware/liteeth/doc/_build/doctrees/environment.pickle create mode 100644 gateware/liteeth/doc/_build/doctrees/ethmac.doctree create mode 100644 gateware/liteeth/doc/_build/doctrees/ethphy.doctree create mode 100644 gateware/liteeth/doc/_build/doctrees/index.doctree create mode 100644 gateware/liteeth/doc/_build/doctrees/interrupts.doctree create mode 100644 gateware/liteeth/doc/_build/html/.buildinfo create mode 100644 gateware/liteeth/doc/_build/html/_sources/ctrl.rst.txt create mode 100644 gateware/liteeth/doc/_build/html/_sources/ethmac.rst.txt create mode 100644 gateware/liteeth/doc/_build/html/_sources/ethphy.rst.txt create mode 100644 gateware/liteeth/doc/_build/html/_sources/index.rst.txt create mode 100644 gateware/liteeth/doc/_build/html/_sources/interrupts.rst.txt create mode 100644 gateware/liteeth/doc/_build/html/_static/WaveDrom.js create mode 100644 gateware/liteeth/doc/_build/html/_static/alabaster.css create mode 100644 gateware/liteeth/doc/_build/html/_static/basic.css create mode 100644 gateware/liteeth/doc/_build/html/_static/custom.css create mode 100644 gateware/liteeth/doc/_build/html/_static/default.js create mode 100644 gateware/liteeth/doc/_build/html/_static/doctools.js create mode 100644 gateware/liteeth/doc/_build/html/_static/documentation_options.js create mode 100644 gateware/liteeth/doc/_build/html/_static/file.png create mode 100644 gateware/liteeth/doc/_build/html/_static/language_data.js create mode 100644 gateware/liteeth/doc/_build/html/_static/minus.png create mode 100644 gateware/liteeth/doc/_build/html/_static/plus.png create mode 100644 gateware/liteeth/doc/_build/html/_static/pygments.css create mode 100644 gateware/liteeth/doc/_build/html/_static/searchtools.js create mode 100644 gateware/liteeth/doc/_build/html/_static/sphinx_highlight.js create mode 100644 gateware/liteeth/doc/_build/html/ctrl.html create mode 100644 gateware/liteeth/doc/_build/html/ethmac.html create mode 100644 gateware/liteeth/doc/_build/html/ethphy.html create mode 100644 gateware/liteeth/doc/_build/html/genindex.html create mode 100644 gateware/liteeth/doc/_build/html/index.html create mode 100644 gateware/liteeth/doc/_build/html/interrupts.html create mode 100644 gateware/liteeth/doc/_build/html/objects.inv create mode 100644 gateware/liteeth/doc/_build/html/search.html create mode 100644 gateware/liteeth/doc/_build/html/searchindex.js create mode 100644 gateware/liteeth/doc/_static/WaveDrom.js create mode 100644 gateware/liteeth/doc/_static/default.js create mode 100644 gateware/liteeth/doc/conf.py create mode 100644 gateware/liteeth/doc/ctrl.rst create mode 100644 gateware/liteeth/doc/ethmac.rst create mode 100644 gateware/liteeth/doc/ethphy.rst create mode 100644 gateware/liteeth/doc/index.rst create mode 100644 gateware/liteeth/doc/interrupts.rst create mode 100644 gateware/liteeth/gateware/build_liteeth_core.sh create mode 100644 gateware/liteeth/gateware/liteeth_core.lpf create mode 100644 gateware/liteeth/gateware/liteeth_core.v create mode 100644 gateware/liteeth/gateware/liteeth_core.ys create mode 100644 gateware/liteeth/software/include/generated/csr.h create mode 100644 gateware/liteeth/software/include/generated/git.h create mode 100644 gateware/liteeth/software/include/generated/mem.h create mode 100644 gateware/liteeth/software/include/generated/soc.h create mode 100644 gateware/test.gtwk diff --git a/gateware/docs/sampler_clock_design.md b/gateware/docs/sampler_clock_design.md new file mode 100644 index 0000000..52a92fd --- /dev/null +++ b/gateware/docs/sampler_clock_design.md @@ -0,0 +1,40 @@ +# Sampler clock design and CDC considerations + +Essentially, I have to support two clock domains, one for the ADC sampling +itself and one for system clock, otherwise we'll have issues pushing the +bandwidth we need to export the data. + +Sampling speed will be 10MHz, as limited by memory resources. Ideally the system +clock will be 50MHz, but 40MHz is a decent minimum IMO. + +The sampler module itself will operate on system clock, with a wishbone +interface. It will pass the sample clock into smaller sub-modules that read the +data from the ADCs. (TODO I need to figure out how to deal with how exactly to +sample the data pins relative to the clock, make sure the signal is stable when +I clock it in. Maybe do negative edge? Idk.) + +- Control signals to the ADC (DFS, 3-STATE, REFSENSE), will be directly wired to + control registers. +- STBY will be controlled by the sampler module +- OTR will be synchronized in to sysclk with n-FF, it is clocked to 10MHz domain + +An enable signal will be synchronized in to the sample clock domain, and that +will be used by the sampler submodules to pull STBY high, and begin sampling. +The sampling submodules will be very dumb, and export the data as determined by +the enable signal, (i.e. wait 5 clocks to start/stop to manage ADC pipeline +latency). + +The data will be synchronized straight through, data connected comb, and a +toggled pin to synchronize the data into sysclk. We can export at full speed if +we latch data in on a change in the toggle pin instead of setting high and +waiting for it to go low. (Otherwise we need to implement some sort of gearing +to push multiple samples through every few sample clocks.) This is okay for CDC +because sysclk is faster than sample clock, so any transition will last long +enough to propogate through the synchronizers, and when we get a change through +the synchronyzer, we can know that the data is valid. This assumes sysclk is at +least 4x faster than the sample clock, so the toggle pin can propogate through +the synchronizer, and the data is still valid before the next sample clock edge. + +On the sysclk side, the toggle will turn into a strobe and data will feed into +circular buffers to store the ping data. It will also be exported to the peak +detector module. diff --git a/gateware/eth.py b/gateware/eth.py index 787e707..3c65008 100644 --- a/gateware/eth.py +++ b/gateware/eth.py @@ -1,27 +1,72 @@ from amaranth import * +from amaranth.lib.io import pin_layout from amaranth_soc.wishbone.bus import Interface + +__all__ = ["LiteEth", "rgmii_layout"] + + # TODO maybe this should just call liteeth_gen to close the loop? class LiteEth(Elaboratable, Interface): def __init__(self): - # TODO change ADDR width - Interface.__init__(self, addr_width=32, data_width=32) + # Addr width is 13 bits to accomodate 0x1FFF, which is well p + Interface.__init__(self, addr_width=13, data_width=32, granularity=8, features=["cti", "bte", "err"]) self.rgmii_eth_clocks_tx = Signal() + self.interrupt = Signal() + + # TODO this really shouldn't technically happen here, because we can elaborate one module multiple times, + # but since I use it once it isn't actually a problem. def elaborate(self, platform): platform.add_file("liteeth_core.v", open("liteeth/gateware/liteeth_core.v", 'r').read()) m = Module() + + # TODO I have to provide TX/RX clocks myself core = Instance( "liteeth_core", i_sys_clock=ClockSignal(), + + # RGMII signals o_rgmii_eth_clocks_tx=self.rgmii_eth_clocks_tx, + + # Wishbone all the things + i_wishbone_adr=self.adr, + i_wishbone_dat_w=self.dat_w, + o_wishbone_dat_r=self.dat_r, + i_wishbone_sel=self.sel, + i_wishbone_cyc=self.cyc, + o_wishbone_ack=self.ack, + i_wishbone_we=self.we, + i_wishbone_cti=self.cti, + i_wishbone_bte=self.bte, + o_wishbone_err=self.err, + + o_interrupt=self.interrupt, ) m.submodules.core = core - return m \ No newline at end of file + return m + + +rgmii_layout = [ + ("clocks_tx", pin_layout(1, "o")), + ("clocks_rx", pin_layout(1, "i")), + ("rst_n", pin_layout(1, "o")), + ("int_n", pin_layout(1, "i")), + + # TODO is this not IO? why does LiteEth say input? + # I think the answer is it uses a primitive, not 100% right now + ("mdio", pin_layout(1, "i")), + ("mdc", pin_layout(1, "o")), + ("rx_ctl", pin_layout(1, "i")), + ("rx_data", pin_layout(4, "i")), + ("tx_ctl", pin_layout(1, "o")), + ("tx_data", pin_layout(4, "o")), +] + diff --git a/gateware/gen_liteeth.sh b/gateware/gen_liteeth.sh old mode 100644 new mode 100755 index e6104cf..dd9e3e6 --- a/gateware/gen_liteeth.sh +++ b/gateware/gen_liteeth.sh @@ -1,3 +1,3 @@ #!/usr/bin/env sh -liteeth_gen --output-dir liteeth liteeth_config.yaml \ No newline at end of file +liteeth_gen --output-dir liteeth --doc liteeth_config.yaml \ No newline at end of file diff --git a/gateware/liteeth/csr.csv b/gateware/liteeth/csr.csv new file mode 100644 index 0000000..a245b9c --- /dev/null +++ b/gateware/liteeth/csr.csv @@ -0,0 +1,45 @@ +#-------------------------------------------------------------------------------- +# Auto-generated by LiteX (8159b5ca) on 2023-02-07 21:33:18 +#-------------------------------------------------------------------------------- +csr_base,ctrl,0x00000000,, +csr_base,ethmac,0x00000800,, +csr_base,ethphy,0x00001000,, +csr_register,ctrl_reset,0x00000000,1,rw +csr_register,ctrl_scratch,0x00000004,1,rw +csr_register,ctrl_bus_errors,0x00000008,1,ro +csr_register,ethmac_sram_writer_slot,0x00000800,1,ro +csr_register,ethmac_sram_writer_length,0x00000804,1,ro +csr_register,ethmac_sram_writer_errors,0x00000808,1,ro +csr_register,ethmac_sram_writer_ev_status,0x0000080c,1,ro +csr_register,ethmac_sram_writer_ev_pending,0x00000810,1,rw +csr_register,ethmac_sram_writer_ev_enable,0x00000814,1,rw +csr_register,ethmac_sram_reader_start,0x00000818,1,rw +csr_register,ethmac_sram_reader_ready,0x0000081c,1,ro +csr_register,ethmac_sram_reader_level,0x00000820,1,ro +csr_register,ethmac_sram_reader_slot,0x00000824,1,rw +csr_register,ethmac_sram_reader_length,0x00000828,1,rw +csr_register,ethmac_sram_reader_ev_status,0x0000082c,1,ro +csr_register,ethmac_sram_reader_ev_pending,0x00000830,1,rw +csr_register,ethmac_sram_reader_ev_enable,0x00000834,1,rw +csr_register,ethmac_preamble_crc,0x00000838,1,ro +csr_register,ethmac_rx_datapath_preamble_errors,0x0000083c,1,ro +csr_register,ethmac_rx_datapath_crc_errors,0x00000840,1,ro +csr_register,ethphy_crg_reset,0x00001000,1,rw +csr_register,ethphy_rx_inband_status,0x00001004,1,ro +csr_register,ethphy_mdio_w,0x00001008,1,rw +csr_register,ethphy_mdio_r,0x0000100c,1,ro +constant,config_clock_frequency,10000000,, +constant,config_cpu_type_none,None,, +constant,config_cpu_variant_standard,None,, +constant,config_cpu_human_name,unknown,, +constant,config_csr_data_width,32,, +constant,config_csr_alignment,32,, +constant,config_bus_standard,wishbone,, +constant,config_bus_data_width,32,, +constant,config_bus_address_width,32,, +constant,config_bus_bursting,0,, +constant,ethmac_rx_slots,2,, +constant,ethmac_tx_slots,2,, +constant,ethmac_slot_size,2048,, +memory_region,ethmac,0x00020000,8192,io +memory_region,csr,0x00000000,65536,io diff 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zcV|Xor@S@)XlF(~Dy`J6wBMVTH9c9dUDS_27&qx;b}evwW4?EyfwZ4Z>EFT&UuP%C z1*}rYD(rL$(RUZRZM0X6A0@f&W!1)7Pq$k~Byz~Ybd`^x)sXq`2h})oc5r85;lG(k z9-Qsti+nHInC?aX2zhbdP|g0~pkM!0&j;Pt_1NdV_Kx!H&U@WG_-*}HJs*@4*Z)RX zVKIAf_8X|L-ZqDHP@` | :ref:`0x00000000 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_SCRATCH ` | :ref:`0x00000004 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_BUS_ERRORS ` | :ref:`0x00000008 ` | ++------------------------------------------+-------------------------------------+ + +CTRL_RESET +^^^^^^^^^^ + +`Address: 0x00000000 + 0x0 = 0x00000000` + + + .. wavedrom:: + :caption: CTRL_RESET + + { + "reg": [ + {"name": "soc_rst", "type": 4, "bits": 1}, + {"name": "cpu_rst", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------+------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+=========+========================================================================+ +| [0] | SOC_RST | Write `1` to this register to reset the full SoC (Pulse Reset) | ++-------+---------+------------------------------------------------------------------------+ +| [1] | CPU_RST | Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset) | ++-------+---------+------------------------------------------------------------------------+ + +CTRL_SCRATCH +^^^^^^^^^^^^ + +`Address: 0x00000000 + 0x4 = 0x00000004` + + Use this register as a scratch space to verify that software read/write accesses + to the Wishbone/CSR bus are working correctly. The initial reset value of + 0x1234578 can be used to verify endianness. + + .. wavedrom:: + :caption: CTRL_SCRATCH + + { + "reg": [ + {"name": "scratch[31:0]", "attr": 'reset: 305419896', "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +CTRL_BUS_ERRORS +^^^^^^^^^^^^^^^ + +`Address: 0x00000000 + 0x8 = 0x00000008` + + Total number of Wishbone bus errors (timeouts) since start. + + .. wavedrom:: + :caption: CTRL_BUS_ERRORS + + { + "reg": [ + {"name": "bus_errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/gateware/liteeth/doc/_build/html/_sources/ethmac.rst.txt b/gateware/liteeth/doc/_build/html/_sources/ethmac.rst.txt new file mode 100644 index 0000000..b644a1f --- /dev/null +++ b/gateware/liteeth/doc/_build/html/_sources/ethmac.rst.txt @@ -0,0 +1,380 @@ +ETHMAC +====== + +Register Listing for ETHMAC +--------------------------- + ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| Register | Address | ++================================================================================+========================================================+ +| :ref:`ETHMAC_SRAM_WRITER_SLOT ` | :ref:`0x00000800 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_WRITER_LENGTH ` | :ref:`0x00000804 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_WRITER_ERRORS ` | :ref:`0x00000808 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_WRITER_EV_STATUS ` | :ref:`0x0000080c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_WRITER_EV_PENDING ` | :ref:`0x00000810 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_WRITER_EV_ENABLE ` | :ref:`0x00000814 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_START ` | :ref:`0x00000818 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_READY ` | :ref:`0x0000081c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_LEVEL ` | :ref:`0x00000820 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_SLOT ` | :ref:`0x00000824 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_LENGTH ` | :ref:`0x00000828 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_EV_STATUS ` | :ref:`0x0000082c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_EV_PENDING ` | :ref:`0x00000830 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_EV_ENABLE ` | :ref:`0x00000834 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_PREAMBLE_CRC ` | :ref:`0x00000838 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_RX_DATAPATH_PREAMBLE_ERRORS ` | :ref:`0x0000083c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_RX_DATAPATH_CRC_ERRORS ` | :ref:`0x00000840 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ + +ETHMAC_SRAM_WRITER_SLOT +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x0 = 0x00000800` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_WRITER_SLOT + + { + "reg": [ + {"name": "sram_writer_slot", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHMAC_SRAM_WRITER_LENGTH +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x4 = 0x00000804` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_WRITER_LENGTH + + { + "reg": [ + {"name": "sram_writer_length[10:0]", "bits": 11}, + {"bits": 21}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ETHMAC_SRAM_WRITER_ERRORS +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x8 = 0x00000808` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_WRITER_ERRORS + + { + "reg": [ + {"name": "sram_writer_errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ETHMAC_SRAM_WRITER_EV_STATUS +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0xc = 0x0000080c` + + This register contains the current raw level of the available event trigger. + Writes to this register have no effect. + + .. wavedrom:: + :caption: ETHMAC_SRAM_WRITER_EV_STATUS + + { + "reg": [ + {"name": "available", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+-----------+----------------------------------+ +| Field | Name | Description | ++=======+===========+==================================+ +| [0] | AVAILABLE | Level of the ``available`` event | ++-------+-----------+----------------------------------+ + +ETHMAC_SRAM_WRITER_EV_PENDING +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x10 = 0x00000810` + + When a available event occurs, the corresponding bit will be set in this + register. To clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: ETHMAC_SRAM_WRITER_EV_PENDING + + { + "reg": [ + {"name": "available", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+-----------+---------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+===========+=================================================================================+ +| [0] | AVAILABLE | `1` if a `available` event occurred. This Event is **level triggered** when the | +| | | signal is **high**. | ++-------+-----------+---------------------------------------------------------------------------------+ + +ETHMAC_SRAM_WRITER_EV_ENABLE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x14 = 0x00000814` + + This register enables the corresponding available events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: ETHMAC_SRAM_WRITER_EV_ENABLE + + { + "reg": [ + {"name": "available", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+-----------+-------------------------------------------------+ +| Field | Name | Description | ++=======+===========+=================================================+ +| [0] | AVAILABLE | Write a ``1`` to enable the ``available`` Event | ++-------+-----------+-------------------------------------------------+ + +ETHMAC_SRAM_READER_START +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x18 = 0x00000818` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_START + + { + "reg": [ + {"name": "sram_reader_start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHMAC_SRAM_READER_READY +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x1c = 0x0000081c` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_READY + + { + "reg": [ + {"name": "sram_reader_ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHMAC_SRAM_READER_LEVEL +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x20 = 0x00000820` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_LEVEL + + { + "reg": [ + {"name": "sram_reader_level[1:0]", "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHMAC_SRAM_READER_SLOT +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x24 = 0x00000824` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_SLOT + + { + "reg": [ + {"name": "sram_reader_slot", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHMAC_SRAM_READER_LENGTH +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x28 = 0x00000828` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_LENGTH + + { + "reg": [ + {"name": "sram_reader_length[10:0]", "bits": 11}, + {"bits": 21}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ETHMAC_SRAM_READER_EV_STATUS +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x2c = 0x0000082c` + + This register contains the current raw level of the event0 event trigger. + Writes to this register have no effect. + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_EV_STATUS + + { + "reg": [ + {"name": "event0", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+--------+-------------------------------+ +| Field | Name | Description | ++=======+========+===============================+ +| [0] | EVENT0 | Level of the ``event0`` event | ++-------+--------+-------------------------------+ + +ETHMAC_SRAM_READER_EV_PENDING +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x30 = 0x00000830` + + When a event0 event occurs, the corresponding bit will be set in this register. + To clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_EV_PENDING + + { + "reg": [ + {"name": "event0", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+--------+----------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+========+==================================================================================+ +| [0] | EVENT0 | `1` if a this particular event occurred. This Event is triggered on a **rising** | +| | | edge. | ++-------+--------+----------------------------------------------------------------------------------+ + +ETHMAC_SRAM_READER_EV_ENABLE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x34 = 0x00000834` + + This register enables the corresponding event0 events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_EV_ENABLE + + { + "reg": [ + {"name": "event0", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+--------+----------------------------------------------+ +| Field | Name | Description | ++=======+========+==============================================+ +| [0] | EVENT0 | Write a ``1`` to enable the ``event0`` Event | ++-------+--------+----------------------------------------------+ + +ETHMAC_PREAMBLE_CRC +^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x38 = 0x00000838` + + + .. wavedrom:: + :caption: ETHMAC_PREAMBLE_CRC + + { + "reg": [ + {"name": "preamble_crc", "attr": 'reset: 1', "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHMAC_RX_DATAPATH_PREAMBLE_ERRORS +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x3c = 0x0000083c` + + + .. wavedrom:: + :caption: ETHMAC_RX_DATAPATH_PREAMBLE_ERRORS + + { + "reg": [ + {"name": "rx_datapath_preamble_errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ETHMAC_RX_DATAPATH_CRC_ERRORS +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x40 = 0x00000840` + + + .. wavedrom:: + :caption: ETHMAC_RX_DATAPATH_CRC_ERRORS + + { + "reg": [ + {"name": "rx_datapath_crc_errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/gateware/liteeth/doc/_build/html/_sources/ethphy.rst.txt b/gateware/liteeth/doc/_build/html/_sources/ethphy.rst.txt new file mode 100644 index 0000000..49c8d6f --- /dev/null +++ b/gateware/liteeth/doc/_build/html/_sources/ethphy.rst.txt @@ -0,0 +1,138 @@ +ETHPHY +====== + +Register Listing for ETHPHY +--------------------------- + ++----------------------------------------------------------+---------------------------------------------+ +| Register | Address | ++==========================================================+=============================================+ +| :ref:`ETHPHY_CRG_RESET ` | :ref:`0x00001000 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`ETHPHY_RX_INBAND_STATUS ` | :ref:`0x00001004 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`ETHPHY_MDIO_W ` | :ref:`0x00001008 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`ETHPHY_MDIO_R ` | :ref:`0x0000100c ` | ++----------------------------------------------------------+---------------------------------------------+ + +ETHPHY_CRG_RESET +^^^^^^^^^^^^^^^^ + +`Address: 0x00001000 + 0x0 = 0x00001000` + + + .. wavedrom:: + :caption: ETHPHY_CRG_RESET + + { + "reg": [ + {"name": "crg_reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHPHY_RX_INBAND_STATUS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00001000 + 0x4 = 0x00001004` + + + .. wavedrom:: + :caption: ETHPHY_RX_INBAND_STATUS + + { + "reg": [ + {"name": "link_status", "bits": 1}, + {"name": "clock_speed", "bits": 1}, + {"name": "duplex_status", "bits": 1}, + {"bits": 29} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------------+-----------------------------------+ +| Field | Name | Description | ++=======+===============+===================================+ +| [0] | LINK_STATUS | | +| | | | +| | | +---------+-------------+ | +| | | | Value | Description | | +| | | +=========+=============+ | +| | | | ``0b0`` | Link down. | | +| | | +---------+-------------+ | +| | | | ``0b1`` | Link up. | | +| | | +---------+-------------+ | ++-------+---------------+-----------------------------------+ +| [1] | CLOCK_SPEED | | +| | | | +| | | +----------+--------------------+ | +| | | | Value | Description | | +| | | +==========+====================+ | +| | | | ``0b00`` | 2.5MHz (10Mbps). | | +| | | +----------+--------------------+ | +| | | | ``0b01`` | 25MHz (100MBps). | | +| | | +----------+--------------------+ | +| | | | ``0b10`` | 125MHz (1000MBps). | | +| | | +----------+--------------------+ | ++-------+---------------+-----------------------------------+ +| [2] | DUPLEX_STATUS | | +| | | | +| | | +---------+--------------+ | +| | | | Value | Description | | +| | | +=========+==============+ | +| | | | ``0b0`` | Half-duplex. | | +| | | +---------+--------------+ | +| | | | ``0b1`` | Full-duplex. | | +| | | +---------+--------------+ | ++-------+---------------+-----------------------------------+ + +ETHPHY_MDIO_W +^^^^^^^^^^^^^ + +`Address: 0x00001000 + 0x8 = 0x00001008` + + + .. wavedrom:: + :caption: ETHPHY_MDIO_W + + { + "reg": [ + {"name": "mdc", "bits": 1}, + {"name": "oe", "bits": 1}, + {"name": "w", "bits": 1}, + {"bits": 29} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ ++-------+------+-------------+ + +ETHPHY_MDIO_R +^^^^^^^^^^^^^ + +`Address: 0x00001000 + 0xc = 0x0000100c` + + + .. wavedrom:: + :caption: ETHPHY_MDIO_R + + { + "reg": [ + {"name": "r", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ + diff --git a/gateware/liteeth/doc/_build/html/_sources/index.rst.txt b/gateware/liteeth/doc/_build/html/_sources/index.rst.txt new file mode 100644 index 0000000..6ffb5f3 --- /dev/null +++ b/gateware/liteeth/doc/_build/html/_sources/index.rst.txt @@ -0,0 +1,31 @@ + +Documentation for LiteX SoC Project +=================================== + + + +Modules +======= + +.. toctree:: + :maxdepth: 1 + + interrupts + +Register Groups +=============== + +.. toctree:: + :maxdepth: 1 + + ctrl + ethmac + ethphy + +Indices and tables +================== + +* :ref:`genindex` +* :ref:`modindex` +* :ref:`search` + diff --git a/gateware/liteeth/doc/_build/html/_sources/interrupts.rst.txt b/gateware/liteeth/doc/_build/html/_sources/interrupts.rst.txt new file mode 100644 index 0000000..9d6df8e --- /dev/null +++ b/gateware/liteeth/doc/_build/html/_sources/interrupts.rst.txt @@ -0,0 +1,18 @@ +Interrupt Controller +==================== + +This device has an ``EventManager``-based interrupt system. Individual modules +generate `events` which are wired into a central interrupt controller. + +When an interrupt occurs, you should look the interrupt number up in the CPU- +specific interrupt table and then call the relevant module. + +Assigned Interrupts +------------------- + +The following interrupts are assigned on this system: + ++-----------+--------+ +| Interrupt | Module | ++===========+========+ + diff --git a/gateware/liteeth/doc/_build/html/_static/WaveDrom.js b/gateware/liteeth/doc/_build/html/_static/WaveDrom.js new file mode 100644 index 0000000..b3d99a6 --- /dev/null +++ b/gateware/liteeth/doc/_build/html/_static/WaveDrom.js @@ -0,0 +1,3 @@ +/*! wavedrom 2.3.2 2020-02-10 */ + +!function o(s,i,c){function l(t,e){if(!i[t]){if(!s[t]){var r="function"==typeof require&&require;if(!e&&r)return r(t,!0);if(u)return u(t,!0);var n=new Error("Cannot find module '"+t+"'");throw n.code="MODULE_NOT_FOUND",n}var a=i[t]={exports:{}};s[t][0].call(a.exports,function(e){return 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+div.sphinxsidebar a:hover { + border-bottom: 1px solid #999; +} + +div.sphinxsidebarwrapper { + padding: 18px 10px; +} + +div.sphinxsidebarwrapper p.logo { + padding: 0; + margin: -10px 0 0 0px; + text-align: center; +} + +div.sphinxsidebarwrapper h1.logo { + margin-top: -10px; + text-align: center; + margin-bottom: 5px; + text-align: left; +} + +div.sphinxsidebarwrapper h1.logo-name { + margin-top: 0px; +} + +div.sphinxsidebarwrapper p.blurb { + margin-top: 0; + font-style: normal; +} + +div.sphinxsidebar h3, +div.sphinxsidebar h4 { + font-family: Georgia, serif; + color: #444; + font-size: 24px; + font-weight: normal; + margin: 0 0 5px 0; + padding: 0; +} + +div.sphinxsidebar h4 { + font-size: 20px; +} + +div.sphinxsidebar h3 a { + color: #444; +} + +div.sphinxsidebar p.logo a, +div.sphinxsidebar h3 a, +div.sphinxsidebar p.logo a:hover, +div.sphinxsidebar h3 a:hover { + border: none; +} + +div.sphinxsidebar p { + color: #555; + margin: 10px 0; +} + +div.sphinxsidebar ul { + margin: 10px 0; + padding: 0; + color: #000; +} + +div.sphinxsidebar ul li.toctree-l1 > a { + font-size: 120%; +} + +div.sphinxsidebar ul li.toctree-l2 > a { + font-size: 110%; +} + +div.sphinxsidebar input { + border: 1px solid #CCC; + font-family: Georgia, serif; + font-size: 1em; +} + +div.sphinxsidebar hr { + border: none; + height: 1px; + color: #AAA; + background: #AAA; + + text-align: left; + margin-left: 0; + width: 50%; +} + +div.sphinxsidebar .badge { + border-bottom: none; +} + +div.sphinxsidebar .badge:hover { + border-bottom: none; +} + +/* To address an issue with donation coming after search */ +div.sphinxsidebar h3.donation { + margin-top: 10px; +} + +/* -- body styles ----------------------------------------------------------- */ + +a { + color: #004B6B; + text-decoration: underline; +} + +a:hover { + color: #6D4100; + text-decoration: underline; +} + +div.body h1, +div.body h2, +div.body h3, +div.body h4, +div.body h5, +div.body h6 { + font-family: Georgia, serif; + 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background-color: #EEE; + border: 1px solid #CCC; +} + +div.topic { + background-color: #EEE; +} + +p.admonition-title { + display: inline; +} + +p.admonition-title:after { + content: ":"; +} + +pre, tt, code { + font-family: 'Consolas', 'Menlo', 'DejaVu Sans Mono', 'Bitstream Vera Sans Mono', monospace; + font-size: 0.9em; +} + +.hll { + background-color: #FFC; + margin: 0 -12px; + padding: 0 12px; + display: block; +} + +img.screenshot { +} + +tt.descname, tt.descclassname, code.descname, code.descclassname { + font-size: 0.95em; +} + +tt.descname, code.descname { + padding-right: 0.08em; +} + +img.screenshot { + -moz-box-shadow: 2px 2px 4px #EEE; + -webkit-box-shadow: 2px 2px 4px #EEE; + box-shadow: 2px 2px 4px #EEE; +} + +table.docutils { + border: 1px solid #888; + -moz-box-shadow: 2px 2px 4px #EEE; + -webkit-box-shadow: 2px 2px 4px #EEE; + box-shadow: 2px 2px 4px #EEE; +} + +table.docutils td, table.docutils th { + border: 1px solid #888; + padding: 0.25em 0.7em; +} + +table.field-list, table.footnote { + border: none; + -moz-box-shadow: none; + -webkit-box-shadow: none; + box-shadow: none; +} + +table.footnote { + margin: 15px 0; + width: 100%; + border: 1px solid #EEE; + background: #FDFDFD; + font-size: 0.9em; +} + +table.footnote + table.footnote { + margin-top: -15px; + border-top: none; +} + +table.field-list th { + padding: 0 0.8em 0 0; +} + +table.field-list td { + padding: 0; +} + +table.field-list p { + margin-bottom: 0.8em; +} + +/* Cloned from + * https://github.com/sphinx-doc/sphinx/commit/ef60dbfce09286b20b7385333d63a60321784e68 + */ +.field-name { + -moz-hyphens: manual; + -ms-hyphens: manual; + -webkit-hyphens: manual; + hyphens: manual; +} + +table.footnote td.label { + width: .1px; + padding: 0.3em 0 0.3em 0.5em; +} + +table.footnote td { + padding: 0.3em 0.5em; +} + +dl { + margin-left: 0; + margin-right: 0; + margin-top: 0; + padding: 0; +} + +dl dd { + margin-left: 30px; +} + +blockquote { + margin: 0 0 0 30px; + padding: 0; +} + +ul, ol { + /* Matches the 30px from the narrow-screen "li > ul" selector below */ + margin: 10px 0 10px 30px; + padding: 0; +} + +pre { + background: #EEE; + padding: 7px 30px; + margin: 15px 0px; + line-height: 1.3em; +} + +div.viewcode-block:target { + background: #ffd; +} + +dl pre, blockquote pre, li pre { + margin-left: 0; + padding-left: 30px; +} + +tt, code { + background-color: #ecf0f3; + color: #222; + /* padding: 1px 2px; */ +} + +tt.xref, code.xref, a tt { + background-color: #FBFBFB; + border-bottom: 1px solid #fff; +} + +a.reference { + text-decoration: none; + border-bottom: 1px dotted #004B6B; +} + +/* Don't put an underline on images */ +a.image-reference, a.image-reference:hover { + border-bottom: none; +} + +a.reference:hover { + border-bottom: 1px solid #6D4100; +} + +a.footnote-reference { + text-decoration: none; + font-size: 0.7em; + vertical-align: top; + border-bottom: 1px dotted #004B6B; +} + +a.footnote-reference:hover { + border-bottom: 1px solid #6D4100; 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background: #333; + color: #FFF; + } + + div.sphinxsidebar h3, div.sphinxsidebar h4, div.sphinxsidebar p, + div.sphinxsidebar h3 a { + color: #fff; + } + + div.sphinxsidebar a { + color: #AAA; + } + + div.sphinxsidebar p.logo { + display: none; + } + + div.document { + width: 100%; + margin: 0; + } + + div.footer { + display: none; + } + + div.bodywrapper { + margin: 0; + } + + div.body { + min-height: 0; + padding: 0; + } + + .rtd_doc_footer { + display: none; + } + + .document { + width: auto; + } + + .footer { + width: auto; + } + + .footer { + width: auto; + } + + .github { + display: none; + } +} + + +/* misc. */ + +.revsys-inline { + display: none!important; +} + +/* Make nested-list/multi-paragraph items look better in Releases changelog + * pages. Without this, docutils' magical list fuckery causes inconsistent + * formatting between different release sub-lists. + */ +div#changelog > div.section > ul > li > p:only-child { + margin-bottom: 0; +} + +/* Hide fugly table cell borders in ..bibliography:: directive output */ +table.docutils.citation, table.docutils.citation td, table.docutils.citation th { + border: none; + /* Below needed in some edge cases; if not applied, bottom shadows appear */ + -moz-box-shadow: none; + -webkit-box-shadow: none; + box-shadow: none; +} + + +/* relbar */ + +.related { + line-height: 30px; + width: 100%; + font-size: 0.9rem; +} + +.related.top { + border-bottom: 1px solid #EEE; + margin-bottom: 20px; +} + +.related.bottom { + border-top: 1px solid #EEE; +} + +.related ul { + padding: 0; + margin: 0; + list-style: none; +} + +.related li { + display: inline; +} + +nav#rellinks { + float: right; +} + +nav#rellinks li+li:before { + content: "|"; +} + +nav#breadcrumbs li+li:before { + content: "\00BB"; +} + +/* Hide certain items when printing */ +@media print { + div.related { + display: none; + } +} \ No newline at end of file diff --git a/gateware/liteeth/doc/_build/html/_static/basic.css b/gateware/liteeth/doc/_build/html/_static/basic.css new file mode 100644 index 0000000..7577acb --- /dev/null +++ b/gateware/liteeth/doc/_build/html/_static/basic.css @@ -0,0 +1,903 @@ +/* + * basic.css + * ~~~~~~~~~ + * + * Sphinx stylesheet -- basic theme. + * + * :copyright: Copyright 2007-2023 by the Sphinx team, see AUTHORS. + * :license: BSD, see LICENSE for details. + * + */ + +/* -- main layout ----------------------------------------------------------- */ + +div.clearer { + clear: both; +} + +div.section::after { + display: block; + content: ''; + clear: left; +} + +/* -- relbar ---------------------------------------------------------------- */ + +div.related { + width: 100%; + font-size: 90%; +} + +div.related h3 { + display: none; +} + +div.related ul { + margin: 0; + padding: 0 0 0 10px; + list-style: none; +} + +div.related li { + display: inline; +} + +div.related li.right { + float: right; + margin-right: 5px; +} + +/* -- sidebar --------------------------------------------------------------- */ + +div.sphinxsidebarwrapper { + padding: 10px 5px 0 10px; +} + +div.sphinxsidebar { + float: left; + width: 230px; + margin-left: -100%; + font-size: 90%; + word-wrap: break-word; + overflow-wrap : break-word; +} + +div.sphinxsidebar ul { + list-style: none; +} + +div.sphinxsidebar ul ul, +div.sphinxsidebar ul.want-points { + margin-left: 20px; + list-style: square; +} + +div.sphinxsidebar ul ul { + margin-top: 0; + margin-bottom: 0; +} + +div.sphinxsidebar form { + margin-top: 10px; +} + +div.sphinxsidebar input { + border: 1px solid #98dbcc; + font-family: sans-serif; + font-size: 1em; +} + +div.sphinxsidebar #searchbox form.search { + overflow: hidden; +} + +div.sphinxsidebar #searchbox input[type="text"] { + float: left; + width: 80%; + padding: 0.25em; + box-sizing: border-box; +} + +div.sphinxsidebar #searchbox input[type="submit"] { + float: left; + width: 20%; + border-left: none; + padding: 0.25em; + box-sizing: border-box; +} + + +img { + border: 0; + max-width: 100%; +} + +/* -- search page ----------------------------------------------------------- */ + +ul.search { + margin: 10px 0 0 20px; + padding: 0; +} + +ul.search li { + padding: 5px 0 5px 20px; + background-image: url(file.png); + background-repeat: no-repeat; + background-position: 0 7px; +} + +ul.search li a { + font-weight: bold; +} + +ul.search li p.context { + color: #888; + margin: 2px 0 0 30px; + text-align: left; +} + +ul.keywordmatches li.goodmatch a { + font-weight: bold; +} + +/* -- index page ------------------------------------------------------------ */ + +table.contentstable { + width: 90%; + margin-left: auto; + margin-right: auto; +} + +table.contentstable p.biglink { + line-height: 150%; +} + +a.biglink { + font-size: 1.3em; +} + +span.linkdescr { + font-style: italic; + padding-top: 5px; + font-size: 90%; +} + +/* -- general index --------------------------------------------------------- */ + +table.indextable { + width: 100%; +} + +table.indextable td { + text-align: left; + vertical-align: top; +} + +table.indextable ul { + margin-top: 0; + margin-bottom: 0; + list-style-type: none; +} + +table.indextable > tbody > tr > td > ul { + padding-left: 0em; +} + +table.indextable tr.pcap { + height: 10px; +} + +table.indextable tr.cap { + margin-top: 10px; + background-color: #f2f2f2; +} + +img.toggler { + margin-right: 3px; + margin-top: 3px; + cursor: pointer; +} + +div.modindex-jumpbox { + border-top: 1px solid #ddd; + border-bottom: 1px solid #ddd; + margin: 1em 0 1em 0; + padding: 0.4em; +} + +div.genindex-jumpbox { + border-top: 1px solid #ddd; + border-bottom: 1px solid #ddd; + margin: 1em 0 1em 0; + padding: 0.4em; +} + +/* -- domain module index --------------------------------------------------- */ + +table.modindextable td { + padding: 2px; + border-collapse: collapse; +} + +/* -- general body styles --------------------------------------------------- */ + +div.body { + min-width: 360px; + max-width: 800px; +} + +div.body p, div.body dd, div.body li, div.body blockquote { + -moz-hyphens: auto; + -ms-hyphens: auto; + -webkit-hyphens: auto; + hyphens: auto; +} + +a.headerlink { + visibility: hidden; +} + +h1:hover > a.headerlink, +h2:hover > a.headerlink, +h3:hover > a.headerlink, +h4:hover > a.headerlink, +h5:hover > a.headerlink, +h6:hover > a.headerlink, +dt:hover > a.headerlink, +caption:hover > a.headerlink, +p.caption:hover > a.headerlink, +div.code-block-caption:hover > a.headerlink { + visibility: visible; +} + +div.body p.caption { + text-align: inherit; +} + +div.body td { + text-align: left; +} + +.first { + margin-top: 0 !important; +} + +p.rubric { + margin-top: 30px; + font-weight: bold; +} + +img.align-left, figure.align-left, .figure.align-left, object.align-left { + clear: left; + float: left; + margin-right: 1em; +} + +img.align-right, figure.align-right, .figure.align-right, object.align-right { + clear: right; + float: right; + margin-left: 1em; +} + +img.align-center, figure.align-center, .figure.align-center, object.align-center { + display: block; + margin-left: auto; + margin-right: auto; +} + +img.align-default, figure.align-default, .figure.align-default { + display: block; + margin-left: auto; + margin-right: auto; +} + +.align-left { + text-align: left; +} + +.align-center { + text-align: center; +} + +.align-default { + text-align: center; +} + +.align-right { + text-align: right; +} + +/* -- sidebars -------------------------------------------------------------- */ + +div.sidebar, +aside.sidebar { + margin: 0 0 0.5em 1em; + border: 1px solid #ddb; + padding: 7px; + background-color: #ffe; + width: 40%; + float: right; + clear: right; + overflow-x: auto; +} + +p.sidebar-title { + font-weight: bold; +} + +nav.contents, +aside.topic, +div.admonition, div.topic, blockquote { + clear: left; +} + +/* -- topics ---------------------------------------------------------------- */ + +nav.contents, +aside.topic, +div.topic { + border: 1px solid #ccc; + padding: 7px; + margin: 10px 0 10px 0; +} + +p.topic-title { + font-size: 1.1em; + font-weight: bold; + margin-top: 10px; +} + +/* -- admonitions ----------------------------------------------------------- */ + +div.admonition { + margin-top: 10px; + margin-bottom: 10px; + padding: 7px; +} + +div.admonition dt { + font-weight: bold; +} + +p.admonition-title { + margin: 0px 10px 5px 0px; + font-weight: bold; +} + +div.body p.centered { + text-align: center; + margin-top: 25px; +} + +/* -- content of sidebars/topics/admonitions -------------------------------- */ + +div.sidebar > :last-child, +aside.sidebar > :last-child, +nav.contents > :last-child, +aside.topic > :last-child, +div.topic > :last-child, +div.admonition > :last-child { + margin-bottom: 0; +} + +div.sidebar::after, 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margin-top: 0px; +} + +th > :last-child, +td > :last-child { + margin-bottom: 0px; +} + +/* -- figures --------------------------------------------------------------- */ + +div.figure, figure { + margin: 0.5em; + padding: 0.5em; +} + +div.figure p.caption, figcaption { + padding: 0.3em; +} + +div.figure p.caption span.caption-number, +figcaption span.caption-number { + font-style: italic; +} + +div.figure p.caption span.caption-text, +figcaption span.caption-text { +} + +/* -- field list styles ----------------------------------------------------- */ + +table.field-list td, table.field-list th { + border: 0 !important; +} + +.field-list ul { + margin: 0; + padding-left: 1em; +} + +.field-list p { + margin: 0; +} + +.field-name { + -moz-hyphens: manual; + -ms-hyphens: manual; + -webkit-hyphens: manual; + hyphens: manual; +} + +/* -- hlist styles ---------------------------------------------------------- */ + +table.hlist { + margin: 1em 0; +} + +table.hlist td { + vertical-align: top; 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JavaScript module for the documentation. + */ +const Documentation = { + init: () => { + Documentation.initDomainIndexTable(); + Documentation.initOnKeyListeners(); + }, + + /** + * i18n support + */ + TRANSLATIONS: {}, + PLURAL_EXPR: (n) => (n === 1 ? 0 : 1), + LOCALE: "unknown", + + // gettext and ngettext don't access this so that the functions + // can safely bound to a different name (_ = Documentation.gettext) + gettext: (string) => { + const translated = Documentation.TRANSLATIONS[string]; + switch (typeof translated) { + case "undefined": + return string; // no translation + case "string": + return translated; // translation exists + default: + return translated[0]; // (singular, plural) translation tuple exists + } + }, + + ngettext: (singular, plural, n) => { + const translated = Documentation.TRANSLATIONS[singular]; + if (typeof translated !== "undefined") + return translated[Documentation.PLURAL_EXPR(n)]; + return n === 1 ? singular : plural; + }, + + addTranslations: (catalog) => { + Object.assign(Documentation.TRANSLATIONS, catalog.messages); + Documentation.PLURAL_EXPR = new Function( + "n", + `return (${catalog.plural_expr})` + ); + Documentation.LOCALE = catalog.locale; + }, + + /** + * helper function to focus on search bar + */ + focusSearchBar: () => { + document.querySelectorAll("input[name=q]")[0]?.focus(); + }, + + /** + * Initialise the domain index toggle buttons + */ + initDomainIndexTable: () => { + const toggler = (el) => { + const idNumber = el.id.substr(7); + const toggledRows = document.querySelectorAll(`tr.cg-${idNumber}`); + if (el.src.substr(-9) === "minus.png") { + el.src = `${el.src.substr(0, el.src.length - 9)}plus.png`; + toggledRows.forEach((el) => (el.style.display = "none")); + } else { + el.src = `${el.src.substr(0, el.src.length - 8)}minus.png`; + toggledRows.forEach((el) => (el.style.display = "")); + } + }; + + const togglerElements = document.querySelectorAll("img.toggler"); + togglerElements.forEach((el) => + el.addEventListener("click", (event) => toggler(event.currentTarget)) + ); + togglerElements.forEach((el) => (el.style.display = "")); + if (DOCUMENTATION_OPTIONS.COLLAPSE_INDEX) togglerElements.forEach(toggler); + }, + + initOnKeyListeners: () => { + // only install a listener if it is really needed + if ( + !DOCUMENTATION_OPTIONS.NAVIGATION_WITH_KEYS && + !DOCUMENTATION_OPTIONS.ENABLE_SEARCH_SHORTCUTS + ) + return; + + document.addEventListener("keydown", (event) => { + // bail for input elements + if (BLACKLISTED_KEY_CONTROL_ELEMENTS.has(document.activeElement.tagName)) return; + // bail with special keys + if (event.altKey || event.ctrlKey || event.metaKey) return; + + if (!event.shiftKey) { + switch (event.key) { + case "ArrowLeft": + if (!DOCUMENTATION_OPTIONS.NAVIGATION_WITH_KEYS) break; + + const prevLink = document.querySelector('link[rel="prev"]'); + if (prevLink && prevLink.href) { + window.location.href = prevLink.href; + event.preventDefault(); + } + break; + case "ArrowRight": + if (!DOCUMENTATION_OPTIONS.NAVIGATION_WITH_KEYS) break; + + const nextLink = document.querySelector('link[rel="next"]'); + if (nextLink && nextLink.href) { + window.location.href = nextLink.href; + event.preventDefault(); + } + break; + } + } + + // some keyboard layouts may need Shift to get / + switch (event.key) { + case "/": + if (!DOCUMENTATION_OPTIONS.ENABLE_SEARCH_SHORTCUTS) break; + Documentation.focusSearchBar(); + event.preventDefault(); + } + }); + }, +}; + +// quick alias for translations +const _ = Documentation.gettext; + +_ready(Documentation.init); diff --git a/gateware/liteeth/doc/_build/html/_static/documentation_options.js b/gateware/liteeth/doc/_build/html/_static/documentation_options.js new file mode 100644 index 0000000..b57ae3b --- /dev/null +++ b/gateware/liteeth/doc/_build/html/_static/documentation_options.js @@ -0,0 +1,14 @@ +var DOCUMENTATION_OPTIONS = { + URL_ROOT: document.getElementById("documentation_options").getAttribute('data-url_root'), + VERSION: '', + LANGUAGE: 'en', + COLLAPSE_INDEX: false, + BUILDER: 'html', + FILE_SUFFIX: '.html', + LINK_SUFFIX: '.html', + HAS_SOURCE: true, + SOURCELINK_SUFFIX: '.txt', + NAVIGATION_WITH_KEYS: false, + SHOW_SEARCH_SUMMARY: true, + ENABLE_SEARCH_SHORTCUTS: true, +}; \ No newline at end of file diff --git a/gateware/liteeth/doc/_build/html/_static/file.png b/gateware/liteeth/doc/_build/html/_static/file.png new file mode 100644 index 0000000000000000000000000000000000000000..a858a410e4faa62ce324d814e4b816fff83a6fb3 GIT binary patch literal 286 zcmV+(0pb3MP)s`hMrGg#P~ix$^RISR_I47Y|r1 z_CyJOe}D1){SET-^Amu_i71Lt6eYfZjRyw@I6OQAIXXHDfiX^GbOlHe=Ae4>0m)d(f|Me07*qoM6N<$f}vM^LjV8( literal 0 HcmV?d00001 diff --git a/gateware/liteeth/doc/_build/html/_static/language_data.js b/gateware/liteeth/doc/_build/html/_static/language_data.js new file mode 100644 index 0000000..250f566 --- /dev/null +++ b/gateware/liteeth/doc/_build/html/_static/language_data.js @@ -0,0 +1,199 @@ +/* + * language_data.js + * ~~~~~~~~~~~~~~~~ + * + * This script contains the language-specific data used by searchtools.js, + * namely the list of stopwords, stemmer, scorer and splitter. + * + * :copyright: Copyright 2007-2023 by the Sphinx team, see AUTHORS. + * :license: BSD, see LICENSE for details. + * + */ + +var stopwords = ["a", "and", "are", "as", "at", "be", "but", "by", "for", "if", "in", "into", "is", "it", "near", "no", "not", "of", "on", "or", "such", "that", "the", "their", "then", "there", "these", "they", "this", "to", "was", "will", "with"]; + + +/* Non-minified version is copied as a separate JS file, is available */ + +/** + * Porter Stemmer + */ +var Stemmer = function() { + + var step2list = { + ational: 'ate', + tional: 'tion', + enci: 'ence', + anci: 'ance', + izer: 'ize', + bli: 'ble', + alli: 'al', + entli: 'ent', + eli: 'e', + ousli: 'ous', + ization: 'ize', + ation: 'ate', + ator: 'ate', + alism: 'al', + iveness: 'ive', + fulness: 'ful', + ousness: 'ous', + aliti: 'al', + iviti: 'ive', + biliti: 'ble', + logi: 'log' + }; + + var step3list = { + icate: 'ic', + ative: '', + alize: 'al', + iciti: 'ic', + ical: 'ic', + ful: '', + ness: '' + }; + + var c = "[^aeiou]"; // consonant + var v = "[aeiouy]"; // vowel + var C = c + "[^aeiouy]*"; // consonant sequence + var V = v + "[aeiou]*"; // vowel sequence + + var mgr0 = "^(" + C + ")?" + V + C; // [C]VC... is m>0 + var meq1 = "^(" + C + ")?" + V + C + "(" + V + ")?$"; // [C]VC[V] is m=1 + var mgr1 = "^(" + C + ")?" + V + C + V + C; // [C]VCVC... is m>1 + var s_v = "^(" + C + ")?" + v; // vowel in stem + + this.stemWord = function (w) { + var stem; + var suffix; + var firstch; + var origword = w; + + if (w.length < 3) + return w; + + var re; + var re2; + var re3; + var re4; + + firstch = w.substr(0,1); + if (firstch == "y") + w = firstch.toUpperCase() + w.substr(1); + + // Step 1a + re = /^(.+?)(ss|i)es$/; + re2 = /^(.+?)([^s])s$/; + + if (re.test(w)) + w = w.replace(re,"$1$2"); + else if (re2.test(w)) + w = w.replace(re2,"$1$2"); + + // Step 1b + re = /^(.+?)eed$/; + re2 = /^(.+?)(ed|ing)$/; + if (re.test(w)) { + var fp = re.exec(w); + re = new RegExp(mgr0); + if (re.test(fp[1])) { + re = /.$/; + w = w.replace(re,""); + } + } + else if (re2.test(w)) { + var fp = re2.exec(w); + stem = fp[1]; + re2 = new RegExp(s_v); + if (re2.test(stem)) { + w = stem; + re2 = /(at|bl|iz)$/; + re3 = new RegExp("([^aeiouylsz])\\1$"); + re4 = new RegExp("^" + C + v + "[^aeiouwxy]$"); + if (re2.test(w)) + w = w + "e"; + else if (re3.test(w)) { + re = /.$/; + w = w.replace(re,""); + } + else if (re4.test(w)) + w = w + "e"; + } + } + + // Step 1c + re = /^(.+?)y$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + re = new RegExp(s_v); + if (re.test(stem)) + w = stem + "i"; + } + + // Step 2 + re = /^(.+?)(ational|tional|enci|anci|izer|bli|alli|entli|eli|ousli|ization|ation|ator|alism|iveness|fulness|ousness|aliti|iviti|biliti|logi)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + suffix = fp[2]; + re = new RegExp(mgr0); + if (re.test(stem)) + w = stem + step2list[suffix]; + } + + // Step 3 + re = /^(.+?)(icate|ative|alize|iciti|ical|ful|ness)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + suffix = fp[2]; + re = new RegExp(mgr0); + if (re.test(stem)) + w = stem + step3list[suffix]; + } + + // Step 4 + re = /^(.+?)(al|ance|ence|er|ic|able|ible|ant|ement|ment|ent|ou|ism|ate|iti|ous|ive|ize)$/; + re2 = /^(.+?)(s|t)(ion)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + re = new RegExp(mgr1); + if (re.test(stem)) + w = stem; + } + else if (re2.test(w)) { + var fp = re2.exec(w); + stem = fp[1] + fp[2]; + re2 = new RegExp(mgr1); + if (re2.test(stem)) + w = stem; + } + + // Step 5 + re = /^(.+?)e$/; + if (re.test(w)) { + var fp = re.exec(w); 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matches in the last dotted part of the object name + objPartialMatch: 6, + // Additive scores depending on the priority of the object + objPrio: { + 0: 15, // used to be importantResults + 1: 5, // used to be objectResults + 2: -5, // used to be unimportantResults + }, + // Used when the priority is not in the mapping. + objPrioDefault: 0, + + // query found in title + title: 15, + partialTitle: 7, + // query found in terms + term: 5, + partialTerm: 2, + }; +} + +const _removeChildren = (element) => { + while (element && element.lastChild) element.removeChild(element.lastChild); +}; + +/** + * See https://developer.mozilla.org/en-US/docs/Web/JavaScript/Guide/Regular_Expressions#escaping + */ +const _escapeRegExp = (string) => + string.replace(/[.*+\-?^${}()|[\]\\]/g, "\\$&"); // $& means the whole matched string + +const _displayItem = (item, searchTerms) => { + const docBuilder = DOCUMENTATION_OPTIONS.BUILDER; + const docUrlRoot = DOCUMENTATION_OPTIONS.URL_ROOT; + const docFileSuffix = DOCUMENTATION_OPTIONS.FILE_SUFFIX; + const docLinkSuffix = DOCUMENTATION_OPTIONS.LINK_SUFFIX; + const showSearchSummary = DOCUMENTATION_OPTIONS.SHOW_SEARCH_SUMMARY; + + const [docName, title, anchor, descr, score, _filename] = item; + + let listItem = document.createElement("li"); + let requestUrl; + let linkUrl; + if (docBuilder === "dirhtml") { + // dirhtml builder + let dirname = docName + "/"; + if (dirname.match(/\/index\/$/)) + dirname = dirname.substring(0, dirname.length - 6); + else if (dirname === "index/") dirname = ""; + requestUrl = docUrlRoot + dirname; + linkUrl = requestUrl; + } else { + // normal html builders + requestUrl = docUrlRoot + docName + docFileSuffix; + linkUrl = docName + docLinkSuffix; + } + let linkEl = listItem.appendChild(document.createElement("a")); + linkEl.href = linkUrl + anchor; + linkEl.dataset.score = score; + linkEl.innerHTML = title; + if (descr) + listItem.appendChild(document.createElement("span")).innerHTML = + " (" + descr + ")"; + else if (showSearchSummary) + fetch(requestUrl) + .then((responseData) => responseData.text()) + .then((data) => { + if (data) + listItem.appendChild( + Search.makeSearchSummary(data, searchTerms) + ); + }); + Search.output.appendChild(listItem); +}; +const _finishSearch = (resultCount) => { + Search.stopPulse(); + Search.title.innerText = _("Search Results"); + if (!resultCount) + Search.status.innerText = Documentation.gettext( + "Your search did not match any documents. Please make sure that all words are spelled correctly and that you've selected enough categories." + ); + else + Search.status.innerText = _( + `Search finished, found ${resultCount} page(s) matching the search query.` + ); +}; +const _displayNextItem = ( + results, + resultCount, + searchTerms +) => { + // results left, load the summary and display it + // this is intended to be dynamic (don't sub resultsCount) + if (results.length) { + _displayItem(results.pop(), searchTerms); + setTimeout( + () => _displayNextItem(results, resultCount, searchTerms), + 5 + ); + } + // search finished, update title and status message + else _finishSearch(resultCount); +}; + +/** + * Default splitQuery function. Can be overridden in ``sphinx.search`` with a + * custom function per language. + * + * The regular expression works by splitting the string on consecutive characters + * that are not Unicode letters, numbers, underscores, or emoji characters. + * This is the same as ``\W+`` in Python, preserving the surrogate pair area. + */ +if (typeof splitQuery === "undefined") { + var splitQuery = (query) => query + .split(/[^\p{Letter}\p{Number}_\p{Emoji_Presentation}]+/gu) + .filter(term => term) // remove remaining empty strings +} + +/** + * Search Module + */ +const Search = { + _index: null, + _queued_query: null, + _pulse_status: -1, + + htmlToText: (htmlString) => { + const htmlElement = new DOMParser().parseFromString(htmlString, 'text/html'); + htmlElement.querySelectorAll(".headerlink").forEach((el) => { el.remove() }); + const docContent = htmlElement.querySelector('[role="main"]'); + if (docContent !== undefined) return docContent.textContent; + console.warn( + "Content block not found. Sphinx search tries to obtain it via '[role=main]'. Could you check your theme or template." + ); + return ""; + }, + + init: () => { + const query = new URLSearchParams(window.location.search).get("q"); + document + .querySelectorAll('input[name="q"]') + .forEach((el) => (el.value = query)); + if (query) Search.performSearch(query); + }, + + loadIndex: (url) => + (document.body.appendChild(document.createElement("script")).src = url), + + setIndex: (index) => { + Search._index = index; + if (Search._queued_query !== null) { + const query = Search._queued_query; + Search._queued_query = null; + Search.query(query); + } + }, + + hasIndex: () => Search._index !== null, + + deferQuery: (query) => (Search._queued_query = query), + + stopPulse: () => (Search._pulse_status = -1), + + startPulse: () => { + if (Search._pulse_status >= 0) return; + + const pulse = () => { + Search._pulse_status = (Search._pulse_status + 1) % 4; + Search.dots.innerText = ".".repeat(Search._pulse_status); + if (Search._pulse_status >= 0) window.setTimeout(pulse, 500); + }; + pulse(); + }, + + /** + * perform a search for something (or wait until index is loaded) + */ + performSearch: (query) => { + // create the required interface elements + const searchText = document.createElement("h2"); + searchText.textContent = _("Searching"); + const searchSummary = document.createElement("p"); + searchSummary.classList.add("search-summary"); + searchSummary.innerText = ""; + const searchList = document.createElement("ul"); + searchList.classList.add("search"); + + const out = document.getElementById("search-results"); + Search.title = out.appendChild(searchText); + Search.dots = Search.title.appendChild(document.createElement("span")); + Search.status = out.appendChild(searchSummary); + Search.output = out.appendChild(searchList); + + const searchProgress = document.getElementById("search-progress"); + // Some themes don't use the search progress node + if (searchProgress) { + searchProgress.innerText = _("Preparing search..."); + } + Search.startPulse(); + + // index already loaded, the browser was quick! + if (Search.hasIndex()) Search.query(query); + else Search.deferQuery(query); + }, + + /** + * execute search (requires search index to be loaded) + */ + query: (query) => { + const filenames = Search._index.filenames; + const docNames = Search._index.docnames; + const titles = Search._index.titles; + const allTitles = Search._index.alltitles; + const indexEntries = Search._index.indexentries; + + // stem the search terms and add them to the correct list + const stemmer = new Stemmer(); + const searchTerms = new Set(); + const excludedTerms = new Set(); + const highlightTerms = new Set(); + const objectTerms = new Set(splitQuery(query.toLowerCase().trim())); + splitQuery(query.trim()).forEach((queryTerm) => { + const queryTermLower = queryTerm.toLowerCase(); + + // maybe skip this "word" + // stopwords array is from language_data.js + if ( + stopwords.indexOf(queryTermLower) !== -1 || + queryTerm.match(/^\d+$/) + ) + return; + + // stem the word + let word = stemmer.stemWord(queryTermLower); + // select the correct list + if (word[0] === "-") excludedTerms.add(word.substr(1)); + else { + searchTerms.add(word); + highlightTerms.add(queryTermLower); + } + }); + + if (SPHINX_HIGHLIGHT_ENABLED) { // set in sphinx_highlight.js + localStorage.setItem("sphinx_highlight_terms", [...highlightTerms].join(" ")) + } + + // console.debug("SEARCH: searching for:"); + // console.info("required: ", [...searchTerms]); + // console.info("excluded: ", [...excludedTerms]); + + // array of [docname, title, anchor, descr, score, filename] + let results = []; + _removeChildren(document.getElementById("search-progress")); + + const queryLower = query.toLowerCase(); + for (const [title, foundTitles] of Object.entries(allTitles)) { + if (title.toLowerCase().includes(queryLower) && (queryLower.length >= title.length/2)) { + for (const [file, id] of foundTitles) { + let score = Math.round(100 * queryLower.length / title.length) + results.push([ + docNames[file], + titles[file] !== title ? `${titles[file]} > ${title}` : title, + id !== null ? "#" + id : "", + null, + score, + filenames[file], + ]); + } + } + } + + // search for explicit entries in index directives + for (const [entry, foundEntries] of Object.entries(indexEntries)) { + if (entry.includes(queryLower) && (queryLower.length >= entry.length/2)) { + for (const [file, id] of foundEntries) { + let score = Math.round(100 * queryLower.length / entry.length) + results.push([ + docNames[file], + titles[file], + id ? "#" + id : "", + null, + score, + filenames[file], + ]); + } + } + } + + // lookup as object + objectTerms.forEach((term) => + results.push(...Search.performObjectSearch(term, objectTerms)) + ); + + // lookup as search terms in fulltext + results.push(...Search.performTermsSearch(searchTerms, excludedTerms)); + + // let the scorer override scores with a custom scoring function + if (Scorer.score) results.forEach((item) => (item[4] = Scorer.score(item))); + + // now sort the results by score (in opposite order of appearance, since the + // display function below uses pop() to retrieve items) and then + // alphabetically + results.sort((a, b) => { + const leftScore = a[4]; + const rightScore = b[4]; + if (leftScore === rightScore) { + // same score: sort alphabetically + const leftTitle = a[1].toLowerCase(); + const rightTitle = b[1].toLowerCase(); + if (leftTitle === rightTitle) return 0; + return leftTitle > rightTitle ? -1 : 1; // inverted is intentional + } + return leftScore > rightScore ? 1 : -1; + }); + + // remove duplicate search results + // note the reversing of results, so that in the case of duplicates, the highest-scoring entry is kept + let seen = new Set(); + results = results.reverse().reduce((acc, result) => { + let resultStr = result.slice(0, 4).concat([result[5]]).map(v => String(v)).join(','); + if (!seen.has(resultStr)) { + acc.push(result); + seen.add(resultStr); + } + return acc; + }, []); + + results = results.reverse(); + + // for debugging + //Search.lastresults = results.slice(); // a copy + // console.info("search results:", Search.lastresults); + + // print the results + _displayNextItem(results, results.length, searchTerms); + }, + + /** + * search for object names + */ + performObjectSearch: (object, objectTerms) => { + const filenames = Search._index.filenames; + const docNames = Search._index.docnames; + const objects = Search._index.objects; + const objNames = Search._index.objnames; + const titles = Search._index.titles; + + const results = []; + + const objectSearchCallback = (prefix, match) => { + const name = match[4] + const fullname = (prefix ? prefix + "." : "") + name; + const fullnameLower = fullname.toLowerCase(); + if (fullnameLower.indexOf(object) < 0) return; + + let score = 0; + const parts = fullnameLower.split("."); + + // check for different match types: exact matches of full name or + // "last name" (i.e. last dotted part) + if (fullnameLower === object || parts.slice(-1)[0] === object) + score += Scorer.objNameMatch; + else if (parts.slice(-1)[0].indexOf(object) > -1) + score += Scorer.objPartialMatch; // matches in last name + + const objName = objNames[match[1]][2]; + const title = titles[match[0]]; + + // If more than one term searched for, we require other words to be + // found in the name/title/description + const otherTerms = new Set(objectTerms); + otherTerms.delete(object); + if (otherTerms.size > 0) { + const haystack = `${prefix} ${name} ${objName} ${title}`.toLowerCase(); + if ( + [...otherTerms].some((otherTerm) => haystack.indexOf(otherTerm) < 0) + ) + return; + } + + let anchor = match[3]; + if (anchor === "") anchor = fullname; + else if (anchor === "-") anchor = objNames[match[1]][1] + "-" + fullname; + + const descr = objName + _(", in ") + title; + + // add custom score for some objects according to scorer + if (Scorer.objPrio.hasOwnProperty(match[2])) + score += Scorer.objPrio[match[2]]; + else score += Scorer.objPrioDefault; + + results.push([ + docNames[match[0]], + fullname, + "#" + anchor, + descr, + score, + filenames[match[0]], + ]); + }; + Object.keys(objects).forEach((prefix) => + objects[prefix].forEach((array) => + objectSearchCallback(prefix, array) + ) + ); + return results; + }, + + /** + * search for full-text terms in the index + */ + performTermsSearch: (searchTerms, excludedTerms) => { + // prepare search + const terms = Search._index.terms; + const titleTerms = Search._index.titleterms; + const filenames = Search._index.filenames; + const docNames = Search._index.docnames; + const titles = Search._index.titles; + + const scoreMap = new Map(); + const fileMap = new Map(); + + // perform the search on the required terms + searchTerms.forEach((word) => { + const files = []; + const arr = [ + { files: terms[word], score: Scorer.term }, + { files: titleTerms[word], score: Scorer.title }, + ]; + // add support for partial matches + if (word.length > 2) { + const escapedWord = _escapeRegExp(word); + Object.keys(terms).forEach((term) => { + if (term.match(escapedWord) && !terms[word]) + arr.push({ files: terms[term], score: Scorer.partialTerm }); + }); + Object.keys(titleTerms).forEach((term) => { + if (term.match(escapedWord) && !titleTerms[word]) + arr.push({ files: titleTerms[word], score: Scorer.partialTitle }); + }); + } + + // no match but word was a required one + if (arr.every((record) => record.files === undefined)) return; + + // found search word in contents + arr.forEach((record) => { + if (record.files === undefined) return; + + let recordFiles = record.files; + if (recordFiles.length === undefined) recordFiles = [recordFiles]; + files.push(...recordFiles); + + // set score for the word in each file + recordFiles.forEach((file) => { + if (!scoreMap.has(file)) scoreMap.set(file, {}); + scoreMap.get(file)[word] = record.score; + }); + }); + + // create the mapping + files.forEach((file) => { + if (fileMap.has(file) && fileMap.get(file).indexOf(word) === -1) + fileMap.get(file).push(word); + else fileMap.set(file, [word]); + }); + }); + + // now check if the files don't contain excluded terms + const results = []; + for (const [file, wordList] of fileMap) { + // check if all requirements are matched + + // as search terms with length < 3 are discarded + const filteredTermCount = [...searchTerms].filter( + (term) => term.length > 2 + ).length; + if ( + wordList.length !== searchTerms.size && + wordList.length !== filteredTermCount + ) + continue; + + // ensure that none of the excluded terms is in the search result + if ( + [...excludedTerms].some( + (term) => + terms[term] === file || + titleTerms[term] === file || + (terms[term] || []).includes(file) || + (titleTerms[term] || []).includes(file) + ) + ) + break; + + // select one (max) score for the file. + const score = Math.max(...wordList.map((w) => scoreMap.get(file)[w])); + // add result to the result list + results.push([ + docNames[file], + titles[file], + "", + null, + score, + filenames[file], + ]); + } + return results; + }, + + /** + * helper function to return a node containing the + * search summary for a given text. keywords is a list + * of stemmed words. + */ + makeSearchSummary: (htmlText, keywords) => { + const text = Search.htmlToText(htmlText); + if (text === "") return null; + + const textLower = text.toLowerCase(); + const actualStartPosition = [...keywords] + .map((k) => textLower.indexOf(k.toLowerCase())) + .filter((i) => i > -1) + .slice(-1)[0]; + const startWithContext = Math.max(actualStartPosition - 120, 0); + + const top = startWithContext === 0 ? "" : "..."; + const tail = startWithContext + 240 < text.length ? "..." : ""; + + let summary = document.createElement("p"); + summary.classList.add("context"); + summary.textContent = top + text.substr(startWithContext, 240).trim() + tail; + + return summary; + }, +}; + +_ready(Search.init); diff --git a/gateware/liteeth/doc/_build/html/_static/sphinx_highlight.js b/gateware/liteeth/doc/_build/html/_static/sphinx_highlight.js new file mode 100644 index 0000000..aae669d --- /dev/null +++ b/gateware/liteeth/doc/_build/html/_static/sphinx_highlight.js @@ -0,0 +1,144 @@ +/* Highlighting utilities for Sphinx HTML documentation. */ +"use strict"; + +const SPHINX_HIGHLIGHT_ENABLED = true + +/** + * highlight a given string on a node by wrapping it in + * span elements with the given class name. + */ +const _highlight = (node, addItems, text, className) => { + if (node.nodeType === Node.TEXT_NODE) { + const val = node.nodeValue; + const parent = node.parentNode; + const pos = val.toLowerCase().indexOf(text); + if ( + pos >= 0 && + !parent.classList.contains(className) && + !parent.classList.contains("nohighlight") + ) { + let span; + + const closestNode = parent.closest("body, svg, foreignObject"); + const isInSVG = closestNode && closestNode.matches("svg"); + if (isInSVG) { + span = document.createElementNS("http://www.w3.org/2000/svg", "tspan"); + } else { + span = document.createElement("span"); + span.classList.add(className); + } + + span.appendChild(document.createTextNode(val.substr(pos, text.length))); + parent.insertBefore( + span, + parent.insertBefore( + document.createTextNode(val.substr(pos + text.length)), + node.nextSibling + ) + ); + node.nodeValue = val.substr(0, pos); + + if (isInSVG) { + const rect = document.createElementNS( + "http://www.w3.org/2000/svg", + "rect" + ); + const bbox = parent.getBBox(); + rect.x.baseVal.value = bbox.x; + rect.y.baseVal.value = bbox.y; + rect.width.baseVal.value = bbox.width; + rect.height.baseVal.value = bbox.height; + rect.setAttribute("class", className); + addItems.push({ parent: parent, target: rect }); + } + } + } else if (node.matches && !node.matches("button, select, textarea")) { + node.childNodes.forEach((el) => _highlight(el, addItems, text, className)); + } +}; +const _highlightText = (thisNode, text, className) => { + let addItems = []; + _highlight(thisNode, addItems, text, className); + addItems.forEach((obj) => + obj.parent.insertAdjacentElement("beforebegin", obj.target) + ); +}; + +/** + * Small JavaScript module for the documentation. + */ +const SphinxHighlight = { + + /** + * highlight the search words provided in localstorage in the text + */ + highlightSearchWords: () => { + if (!SPHINX_HIGHLIGHT_ENABLED) return; // bail if no highlight + + // get and clear terms from localstorage + const url = new URL(window.location); + const highlight = + localStorage.getItem("sphinx_highlight_terms") + || url.searchParams.get("highlight") + || ""; + localStorage.removeItem("sphinx_highlight_terms") + url.searchParams.delete("highlight"); + window.history.replaceState({}, "", url); + + // get individual terms from highlight string + const terms = highlight.toLowerCase().split(/\s+/).filter(x => x); + if (terms.length === 0) return; // nothing to do + + // There should never be more than one element matching "div.body" + const divBody = document.querySelectorAll("div.body"); + const body = divBody.length ? divBody[0] : document.querySelector("body"); + window.setTimeout(() => { + terms.forEach((term) => _highlightText(body, term, "highlighted")); + }, 10); + + const searchBox = document.getElementById("searchbox"); + if (searchBox === null) return; + searchBox.appendChild( + document + .createRange() + .createContextualFragment( + '

' + + '' + + _("Hide Search Matches") + + "

" + ) + ); + }, + + /** + * helper function to hide the search marks again + */ + hideSearchWords: () => { + document + .querySelectorAll("#searchbox .highlight-link") + .forEach((el) => el.remove()); + document + .querySelectorAll("span.highlighted") + .forEach((el) => el.classList.remove("highlighted")); + localStorage.removeItem("sphinx_highlight_terms") + }, + + initEscapeListener: () => { + // only install a listener if it is really needed + if (!DOCUMENTATION_OPTIONS.ENABLE_SEARCH_SHORTCUTS) return; + + document.addEventListener("keydown", (event) => { + // bail for input elements + if (BLACKLISTED_KEY_CONTROL_ELEMENTS.has(document.activeElement.tagName)) return; + // bail with special keys + if (event.shiftKey || event.altKey || event.ctrlKey || event.metaKey) return; + if (DOCUMENTATION_OPTIONS.ENABLE_SEARCH_SHORTCUTS && (event.key === "Escape")) { + SphinxHighlight.hideSearchWords(); + event.preventDefault(); + } + }); + }, +}; + +_ready(SphinxHighlight.highlightSearchWords); +_ready(SphinxHighlight.initEscapeListener); diff --git a/gateware/liteeth/doc/_build/html/ctrl.html b/gateware/liteeth/doc/_build/html/ctrl.html new file mode 100644 index 0000000..8540d10 --- /dev/null +++ b/gateware/liteeth/doc/_build/html/ctrl.html @@ -0,0 +1,213 @@ + + + + + + + + + CTRL — LiteX SoC Project documentation + + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+ +
+

CTRL¶

+
+

Register Listing for CTRL¶

+ + + + + + + + + + + + + + + + + +

Register

Address

CTRL_RESET

0x00000000

CTRL_SCRATCH

0x00000004

CTRL_BUS_ERRORS

0x00000008

+
+

CTRL_RESET¶

+

Address: 0x00000000 + 0x0 = 0x00000000

+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + +

Field

Name

Description

[0]

SOC_RST

Write 1 to this register to reset the full SoC (Pulse Reset)

[1]

CPU_RST

Write 1 to this register to reset the CPU(s) of the SoC (Hold Reset)

+
+
+

CTRL_SCRATCH¶

+

Address: 0x00000000 + 0x4 = 0x00000004

+
+

Use this register as a scratch space to verify that software read/write accesses +to the Wishbone/CSR bus are working correctly. The initial reset value of +0x1234578 can be used to verify endianness.

+ +
+ +
+
+
+
+

CTRL_BUS_ERRORS¶

+

Address: 0x00000000 + 0x8 = 0x00000008

+
+

Total number of Wishbone bus errors (timeouts) since start.

+ +
+ +
+
+
+
+
+ + + +
+ +
+
+ +
+
+
+ ©2023, Anonymous. + + | + Powered by Sphinx 6.1.3 + & Alabaster 0.7.13 + + | + Page source +
+ + + + + + \ No newline at end of file diff --git a/gateware/liteeth/doc/_build/html/ethmac.html b/gateware/liteeth/doc/_build/html/ethmac.html new file mode 100644 index 0000000..b6bcfb5 --- /dev/null +++ b/gateware/liteeth/doc/_build/html/ethmac.html @@ -0,0 +1,567 @@ + + + + + + + + + ETHMAC — LiteX SoC Project documentation + + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+ +
+

ETHMAC¶

+
+

Register Listing for ETHMAC¶

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Register

Address

ETHMAC_SRAM_WRITER_SLOT

0x00000800

ETHMAC_SRAM_WRITER_LENGTH

0x00000804

ETHMAC_SRAM_WRITER_ERRORS

0x00000808

ETHMAC_SRAM_WRITER_EV_STATUS

0x0000080c

ETHMAC_SRAM_WRITER_EV_PENDING

0x00000810

ETHMAC_SRAM_WRITER_EV_ENABLE

0x00000814

ETHMAC_SRAM_READER_START

0x00000818

ETHMAC_SRAM_READER_READY

0x0000081c

ETHMAC_SRAM_READER_LEVEL

0x00000820

ETHMAC_SRAM_READER_SLOT

0x00000824

ETHMAC_SRAM_READER_LENGTH

0x00000828

ETHMAC_SRAM_READER_EV_STATUS

0x0000082c

ETHMAC_SRAM_READER_EV_PENDING

0x00000830

ETHMAC_SRAM_READER_EV_ENABLE

0x00000834

ETHMAC_PREAMBLE_CRC

0x00000838

ETHMAC_RX_DATAPATH_PREAMBLE_ERRORS

0x0000083c

ETHMAC_RX_DATAPATH_CRC_ERRORS

0x00000840

+
+

ETHMAC_SRAM_WRITER_SLOT¶

+

Address: 0x00000800 + 0x0 = 0x00000800

+
+
+
+ +
+
+
+
+

ETHMAC_SRAM_WRITER_LENGTH¶

+

Address: 0x00000800 + 0x4 = 0x00000804

+
+
+
+ +
+
+
+
+

ETHMAC_SRAM_WRITER_ERRORS¶

+

Address: 0x00000800 + 0x8 = 0x00000808

+
+
+
+ +
+
+
+
+

ETHMAC_SRAM_WRITER_EV_STATUS¶

+

Address: 0x00000800 + 0xc = 0x0000080c

+
+

This register contains the current raw level of the available event trigger. +Writes to this register have no effect.

+ +
+ +
+
+ + + + + + + + + + + + + +

Field

Name

Description

[0]

AVAILABLE

Level of the available event

+
+
+

ETHMAC_SRAM_WRITER_EV_PENDING¶

+

Address: 0x00000800 + 0x10 = 0x00000810

+
+

When a available event occurs, the corresponding bit will be set in this +register. To clear the Event, set the corresponding bit in this register.

+ +
+ +
+
+ + + + + + + + + + + + + +

Field

Name

Description

[0]

AVAILABLE

1 if a available event occurred. This Event is level triggered when the +signal is high.

+
+
+

ETHMAC_SRAM_WRITER_EV_ENABLE¶

+

Address: 0x00000800 + 0x14 = 0x00000814

+
+

This register enables the corresponding available events. Write a 0 to this +register to disable individual events.

+ +
+ +
+
+ + + + + + + + + + + + + +

Field

Name

Description

[0]

AVAILABLE

Write a 1 to enable the available Event

+
+
+

ETHMAC_SRAM_READER_START¶

+

Address: 0x00000800 + 0x18 = 0x00000818

+
+
+
+ +
+
+
+
+

ETHMAC_SRAM_READER_READY¶

+

Address: 0x00000800 + 0x1c = 0x0000081c

+
+
+
+ +
+
+
+
+

ETHMAC_SRAM_READER_LEVEL¶

+

Address: 0x00000800 + 0x20 = 0x00000820

+
+
+
+ +
+
+
+
+

ETHMAC_SRAM_READER_SLOT¶

+

Address: 0x00000800 + 0x24 = 0x00000824

+
+
+
+ +
+
+
+
+

ETHMAC_SRAM_READER_LENGTH¶

+

Address: 0x00000800 + 0x28 = 0x00000828

+
+
+
+ +
+
+
+
+

ETHMAC_SRAM_READER_EV_STATUS¶

+

Address: 0x00000800 + 0x2c = 0x0000082c

+
+

This register contains the current raw level of the event0 event trigger. +Writes to this register have no effect.

+ +
+ +
+
+ + + + + + + + + + + + + +

Field

Name

Description

[0]

EVENT0

Level of the event0 event

+
+
+

ETHMAC_SRAM_READER_EV_PENDING¶

+

Address: 0x00000800 + 0x30 = 0x00000830

+
+

When a event0 event occurs, the corresponding bit will be set in this register. +To clear the Event, set the corresponding bit in this register.

+ +
+ +
+
+ + + + + + + + + + + + + +

Field

Name

Description

[0]

EVENT0

1 if a this particular event occurred. This Event is triggered on a rising +edge.

+
+
+

ETHMAC_SRAM_READER_EV_ENABLE¶

+

Address: 0x00000800 + 0x34 = 0x00000834

+
+

This register enables the corresponding event0 events. Write a 0 to this +register to disable individual events.

+ +
+ +
+
+ + + + + + + + + + + + + +

Field

Name

Description

[0]

EVENT0

Write a 1 to enable the event0 Event

+
+
+

ETHMAC_PREAMBLE_CRC¶

+

Address: 0x00000800 + 0x38 = 0x00000838

+
+
+
+ +
+
+
+
+

ETHMAC_RX_DATAPATH_PREAMBLE_ERRORS¶

+

Address: 0x00000800 + 0x3c = 0x0000083c

+
+
+
+ +
+
+
+
+

ETHMAC_RX_DATAPATH_CRC_ERRORS¶

+

Address: 0x00000800 + 0x40 = 0x00000840

+
+
+
+ +
+
+
+
+
+ + + +
+ +
+
+ +
+
+
+ ©2023, Anonymous. + + | + Powered by Sphinx 6.1.3 + & Alabaster 0.7.13 + + | + Page source +
+ + + + + + \ No newline at end of file diff --git a/gateware/liteeth/doc/_build/html/ethphy.html b/gateware/liteeth/doc/_build/html/ethphy.html new file mode 100644 index 0000000..d71e986 --- /dev/null +++ b/gateware/liteeth/doc/_build/html/ethphy.html @@ -0,0 +1,320 @@ + + + + + + + + + ETHPHY — LiteX SoC Project documentation + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+ +
+

ETHPHY¶

+
+

Register Listing for ETHPHY¶

+ + + + + + + + + + + + + + + + + + + + +

Register

Address

ETHPHY_CRG_RESET

0x00001000

ETHPHY_RX_INBAND_STATUS

0x00001004

ETHPHY_MDIO_W

0x00001008

ETHPHY_MDIO_R

0x0000100c

+
+

ETHPHY_CRG_RESET¶

+

Address: 0x00001000 + 0x0 = 0x00001000

+
+
+
+ +
+
+
+
+

ETHPHY_RX_INBAND_STATUS¶

+

Address: 0x00001000 + 0x4 = 0x00001004

+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + +

Field

Name

Description

[0]

LINK_STATUS

 + + + + + + + + + + + + + +

Value

Description

0b0

Link down.

0b1

Link up.

+

[1]

CLOCK_SPEED

 + + + + + + + + + + + + + + + + +

Value

Description

0b00

2.5MHz (10Mbps).

0b01

25MHz (100MBps).

0b10

125MHz (1000MBps).

+

[2]

DUPLEX_STATUS

 + + + + + + + + + + + + + +

Value

Description

0b0

Half-duplex.

0b1

Full-duplex.

+
+
+
+

ETHPHY_MDIO_W¶

+

Address: 0x00001000 + 0x8 = 0x00001008

+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + +

Field

Name

Description

+
+
+

ETHPHY_MDIO_R¶

+

Address: 0x00001000 + 0xc = 0x0000100c

+
+
+
+ +
+
+ + + + + + + + + + + + + +

Field

Name

Description

+
+
+
+ + + +
+ +
+
+ +
+
+
+ ©2023, Anonymous. + + | + Powered by Sphinx 6.1.3 + & Alabaster 0.7.13 + + | + Page source +
+ + + + + + \ No newline at end of file diff --git a/gateware/liteeth/doc/_build/html/genindex.html b/gateware/liteeth/doc/_build/html/genindex.html new file mode 100644 index 0000000..781e50b --- /dev/null +++ b/gateware/liteeth/doc/_build/html/genindex.html @@ -0,0 +1,109 @@ + + + + + + + + Index — LiteX SoC Project documentation + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+ + +

Index

+ +
+ +
+ + +
+ +
+
+ +
+
+
+ ©2023, Anonymous. + + | + Powered by Sphinx 6.1.3 + & Alabaster 0.7.13 + +
+ + + + + + \ No newline at end of file diff --git a/gateware/liteeth/doc/_build/html/index.html b/gateware/liteeth/doc/_build/html/index.html new file mode 100644 index 0000000..8170db6 --- /dev/null +++ b/gateware/liteeth/doc/_build/html/index.html @@ -0,0 +1,144 @@ + + + + + + + + + Documentation for LiteX SoC Project — LiteX SoC Project documentation + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+ +
+

Documentation for LiteX SoC Project¶

+
+
+

Modules¶

+
+ +
+
+
+

Register Groups¶

+
+ +
+
+
+

Indices and tables¶

+ +
+ + + +
+ +
+
+ +
+
+
+ ©2023, Anonymous. + + | + Powered by Sphinx 6.1.3 + & Alabaster 0.7.13 + + | + Page source +
+ + + + + + \ No newline at end of file diff --git a/gateware/liteeth/doc/_build/html/interrupts.html b/gateware/liteeth/doc/_build/html/interrupts.html new file mode 100644 index 0000000..f8e1012 --- /dev/null +++ b/gateware/liteeth/doc/_build/html/interrupts.html @@ -0,0 +1,128 @@ + + + + + + + + + Interrupt Controller — LiteX SoC Project documentation + + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+ +
+

Interrupt Controller¶

+

This device has an EventManager-based interrupt system. Individual modules +generate events which are wired into a central interrupt controller.

+

When an interrupt occurs, you should look the interrupt number up in the CPU- +specific interrupt table and then call the relevant module.

+
+

Assigned Interrupts¶

+

The following interrupts are assigned on this system:

+
+
+ + + +
+ +
+
+ +
+
+
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+
+
+ + +
+ +

Search

+ + + + +

+ Searching for multiple words only shows matches that contain + all words. +

+ + +
+ + + +
+ + + +
+ +
+ + +
+ +
+
+ +
+
+
+ ©2023, Anonymous. + + | + Powered by Sphinx 6.1.3 + & Alabaster 0.7.13 + +
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8","refX":"-15","refY":"0","orient":"auto"},["path",{"d":"M0 -4 -11 0 0 4z"}]]],["g",{"id":"waves"},["g",{"id":"lanes"}],["g",{"id":"groups"}]]]; +try { module.exports = WaveSkin; } catch(err) {} + diff --git a/gateware/liteeth/doc/conf.py b/gateware/liteeth/doc/conf.py new file mode 100644 index 0000000..a0f4668 --- /dev/null +++ b/gateware/liteeth/doc/conf.py @@ -0,0 +1,17 @@ + +project = 'LiteX SoC Project' +copyright = '2023, Anonymous' +author = 'Anonymous' +extensions = [ + 'sphinx.ext.autosectionlabel', + 'sphinxcontrib.wavedrom', +] +templates_path = ['_templates'] +exclude_patterns = [] +offline_skin_js_path = "https://wavedrom.com/skins/default.js" +offline_wavedrom_js_path = "https://wavedrom.com/WaveDrom.js" +html_theme = 'alabaster' +html_static_path = ['_static'] +master_doc = 'index' + + diff --git a/gateware/liteeth/doc/ctrl.rst b/gateware/liteeth/doc/ctrl.rst new file mode 100644 index 0000000..adcb055 --- /dev/null +++ b/gateware/liteeth/doc/ctrl.rst @@ -0,0 +1,78 @@ +CTRL +==== + +Register Listing for CTRL +------------------------- + ++------------------------------------------+-------------------------------------+ +| Register | Address | ++==========================================+=====================================+ +| :ref:`CTRL_RESET ` | :ref:`0x00000000 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_SCRATCH ` | :ref:`0x00000004 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_BUS_ERRORS ` | :ref:`0x00000008 ` | ++------------------------------------------+-------------------------------------+ + +CTRL_RESET +^^^^^^^^^^ + +`Address: 0x00000000 + 0x0 = 0x00000000` + + + .. wavedrom:: + :caption: CTRL_RESET + + { + "reg": [ + {"name": "soc_rst", "type": 4, "bits": 1}, + {"name": "cpu_rst", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------+------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+=========+========================================================================+ +| [0] | SOC_RST | Write `1` to this register to reset the full SoC (Pulse Reset) | ++-------+---------+------------------------------------------------------------------------+ +| [1] | CPU_RST | Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset) | ++-------+---------+------------------------------------------------------------------------+ + +CTRL_SCRATCH +^^^^^^^^^^^^ + +`Address: 0x00000000 + 0x4 = 0x00000004` + + Use this register as a scratch space to verify that software read/write accesses + to the Wishbone/CSR bus are working correctly. The initial reset value of + 0x1234578 can be used to verify endianness. + + .. wavedrom:: + :caption: CTRL_SCRATCH + + { + "reg": [ + {"name": "scratch[31:0]", "attr": 'reset: 305419896', "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +CTRL_BUS_ERRORS +^^^^^^^^^^^^^^^ + +`Address: 0x00000000 + 0x8 = 0x00000008` + + Total number of Wishbone bus errors (timeouts) since start. + + .. wavedrom:: + :caption: CTRL_BUS_ERRORS + + { + "reg": [ + {"name": "bus_errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/gateware/liteeth/doc/ethmac.rst b/gateware/liteeth/doc/ethmac.rst new file mode 100644 index 0000000..b644a1f --- /dev/null +++ b/gateware/liteeth/doc/ethmac.rst @@ -0,0 +1,380 @@ +ETHMAC +====== + +Register Listing for ETHMAC +--------------------------- + ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| Register | Address | ++================================================================================+========================================================+ +| :ref:`ETHMAC_SRAM_WRITER_SLOT ` | :ref:`0x00000800 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_WRITER_LENGTH ` | :ref:`0x00000804 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_WRITER_ERRORS ` | :ref:`0x00000808 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_WRITER_EV_STATUS ` | :ref:`0x0000080c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_WRITER_EV_PENDING ` | :ref:`0x00000810 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_WRITER_EV_ENABLE ` | :ref:`0x00000814 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_START ` | :ref:`0x00000818 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_READY ` | :ref:`0x0000081c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_LEVEL ` | :ref:`0x00000820 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_SLOT ` | :ref:`0x00000824 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_LENGTH ` | :ref:`0x00000828 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_EV_STATUS ` | :ref:`0x0000082c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_EV_PENDING ` | :ref:`0x00000830 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_SRAM_READER_EV_ENABLE ` | :ref:`0x00000834 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_PREAMBLE_CRC ` | :ref:`0x00000838 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_RX_DATAPATH_PREAMBLE_ERRORS ` | :ref:`0x0000083c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`ETHMAC_RX_DATAPATH_CRC_ERRORS ` | :ref:`0x00000840 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ + +ETHMAC_SRAM_WRITER_SLOT +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x0 = 0x00000800` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_WRITER_SLOT + + { + "reg": [ + {"name": "sram_writer_slot", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHMAC_SRAM_WRITER_LENGTH +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x4 = 0x00000804` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_WRITER_LENGTH + + { + "reg": [ + {"name": "sram_writer_length[10:0]", "bits": 11}, + {"bits": 21}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ETHMAC_SRAM_WRITER_ERRORS +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x8 = 0x00000808` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_WRITER_ERRORS + + { + "reg": [ + {"name": "sram_writer_errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ETHMAC_SRAM_WRITER_EV_STATUS +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0xc = 0x0000080c` + + This register contains the current raw level of the available event trigger. + Writes to this register have no effect. + + .. wavedrom:: + :caption: ETHMAC_SRAM_WRITER_EV_STATUS + + { + "reg": [ + {"name": "available", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+-----------+----------------------------------+ +| Field | Name | Description | ++=======+===========+==================================+ +| [0] | AVAILABLE | Level of the ``available`` event | ++-------+-----------+----------------------------------+ + +ETHMAC_SRAM_WRITER_EV_PENDING +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x10 = 0x00000810` + + When a available event occurs, the corresponding bit will be set in this + register. To clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: ETHMAC_SRAM_WRITER_EV_PENDING + + { + "reg": [ + {"name": "available", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+-----------+---------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+===========+=================================================================================+ +| [0] | AVAILABLE | `1` if a `available` event occurred. This Event is **level triggered** when the | +| | | signal is **high**. | ++-------+-----------+---------------------------------------------------------------------------------+ + +ETHMAC_SRAM_WRITER_EV_ENABLE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x14 = 0x00000814` + + This register enables the corresponding available events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: ETHMAC_SRAM_WRITER_EV_ENABLE + + { + "reg": [ + {"name": "available", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+-----------+-------------------------------------------------+ +| Field | Name | Description | ++=======+===========+=================================================+ +| [0] | AVAILABLE | Write a ``1`` to enable the ``available`` Event | ++-------+-----------+-------------------------------------------------+ + +ETHMAC_SRAM_READER_START +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x18 = 0x00000818` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_START + + { + "reg": [ + {"name": "sram_reader_start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHMAC_SRAM_READER_READY +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x1c = 0x0000081c` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_READY + + { + "reg": [ + {"name": "sram_reader_ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHMAC_SRAM_READER_LEVEL +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x20 = 0x00000820` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_LEVEL + + { + "reg": [ + {"name": "sram_reader_level[1:0]", "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHMAC_SRAM_READER_SLOT +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x24 = 0x00000824` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_SLOT + + { + "reg": [ + {"name": "sram_reader_slot", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHMAC_SRAM_READER_LENGTH +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x28 = 0x00000828` + + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_LENGTH + + { + "reg": [ + {"name": "sram_reader_length[10:0]", "bits": 11}, + {"bits": 21}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ETHMAC_SRAM_READER_EV_STATUS +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x2c = 0x0000082c` + + This register contains the current raw level of the event0 event trigger. + Writes to this register have no effect. + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_EV_STATUS + + { + "reg": [ + {"name": "event0", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+--------+-------------------------------+ +| Field | Name | Description | ++=======+========+===============================+ +| [0] | EVENT0 | Level of the ``event0`` event | ++-------+--------+-------------------------------+ + +ETHMAC_SRAM_READER_EV_PENDING +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x30 = 0x00000830` + + When a event0 event occurs, the corresponding bit will be set in this register. + To clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_EV_PENDING + + { + "reg": [ + {"name": "event0", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+--------+----------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+========+==================================================================================+ +| [0] | EVENT0 | `1` if a this particular event occurred. This Event is triggered on a **rising** | +| | | edge. | ++-------+--------+----------------------------------------------------------------------------------+ + +ETHMAC_SRAM_READER_EV_ENABLE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x34 = 0x00000834` + + This register enables the corresponding event0 events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: ETHMAC_SRAM_READER_EV_ENABLE + + { + "reg": [ + {"name": "event0", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+--------+----------------------------------------------+ +| Field | Name | Description | ++=======+========+==============================================+ +| [0] | EVENT0 | Write a ``1`` to enable the ``event0`` Event | ++-------+--------+----------------------------------------------+ + +ETHMAC_PREAMBLE_CRC +^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x38 = 0x00000838` + + + .. wavedrom:: + :caption: ETHMAC_PREAMBLE_CRC + + { + "reg": [ + {"name": "preamble_crc", "attr": 'reset: 1', "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHMAC_RX_DATAPATH_PREAMBLE_ERRORS +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x3c = 0x0000083c` + + + .. wavedrom:: + :caption: ETHMAC_RX_DATAPATH_PREAMBLE_ERRORS + + { + "reg": [ + {"name": "rx_datapath_preamble_errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ETHMAC_RX_DATAPATH_CRC_ERRORS +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00000800 + 0x40 = 0x00000840` + + + .. wavedrom:: + :caption: ETHMAC_RX_DATAPATH_CRC_ERRORS + + { + "reg": [ + {"name": "rx_datapath_crc_errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/gateware/liteeth/doc/ethphy.rst b/gateware/liteeth/doc/ethphy.rst new file mode 100644 index 0000000..49c8d6f --- /dev/null +++ b/gateware/liteeth/doc/ethphy.rst @@ -0,0 +1,138 @@ +ETHPHY +====== + +Register Listing for ETHPHY +--------------------------- + ++----------------------------------------------------------+---------------------------------------------+ +| Register | Address | ++==========================================================+=============================================+ +| :ref:`ETHPHY_CRG_RESET ` | :ref:`0x00001000 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`ETHPHY_RX_INBAND_STATUS ` | :ref:`0x00001004 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`ETHPHY_MDIO_W ` | :ref:`0x00001008 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`ETHPHY_MDIO_R ` | :ref:`0x0000100c ` | ++----------------------------------------------------------+---------------------------------------------+ + +ETHPHY_CRG_RESET +^^^^^^^^^^^^^^^^ + +`Address: 0x00001000 + 0x0 = 0x00001000` + + + .. wavedrom:: + :caption: ETHPHY_CRG_RESET + + { + "reg": [ + {"name": "crg_reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHPHY_RX_INBAND_STATUS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0x00001000 + 0x4 = 0x00001004` + + + .. wavedrom:: + :caption: ETHPHY_RX_INBAND_STATUS + + { + "reg": [ + {"name": "link_status", "bits": 1}, + {"name": "clock_speed", "bits": 1}, + {"name": "duplex_status", "bits": 1}, + {"bits": 29} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------------+-----------------------------------+ +| Field | Name | Description | ++=======+===============+===================================+ +| [0] | LINK_STATUS | | +| | | | +| | | +---------+-------------+ | +| | | | Value | Description | | +| | | +=========+=============+ | +| | | | ``0b0`` | Link down. | | +| | | +---------+-------------+ | +| | | | ``0b1`` | Link up. | | +| | | +---------+-------------+ | ++-------+---------------+-----------------------------------+ +| [1] | CLOCK_SPEED | | +| | | | +| | | +----------+--------------------+ | +| | | | Value | Description | | +| | | +==========+====================+ | +| | | | ``0b00`` | 2.5MHz (10Mbps). | | +| | | +----------+--------------------+ | +| | | | ``0b01`` | 25MHz (100MBps). | | +| | | +----------+--------------------+ | +| | | | ``0b10`` | 125MHz (1000MBps). | | +| | | +----------+--------------------+ | ++-------+---------------+-----------------------------------+ +| [2] | DUPLEX_STATUS | | +| | | | +| | | +---------+--------------+ | +| | | | Value | Description | | +| | | +=========+==============+ | +| | | | ``0b0`` | Half-duplex. | | +| | | +---------+--------------+ | +| | | | ``0b1`` | Full-duplex. | | +| | | +---------+--------------+ | ++-------+---------------+-----------------------------------+ + +ETHPHY_MDIO_W +^^^^^^^^^^^^^ + +`Address: 0x00001000 + 0x8 = 0x00001008` + + + .. wavedrom:: + :caption: ETHPHY_MDIO_W + + { + "reg": [ + {"name": "mdc", "bits": 1}, + {"name": "oe", "bits": 1}, + {"name": "w", "bits": 1}, + {"bits": 29} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ ++-------+------+-------------+ + +ETHPHY_MDIO_R +^^^^^^^^^^^^^ + +`Address: 0x00001000 + 0xc = 0x0000100c` + + + .. wavedrom:: + :caption: ETHPHY_MDIO_R + + { + "reg": [ + {"name": "r", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ + diff --git a/gateware/liteeth/doc/index.rst b/gateware/liteeth/doc/index.rst new file mode 100644 index 0000000..6ffb5f3 --- /dev/null +++ b/gateware/liteeth/doc/index.rst @@ -0,0 +1,31 @@ + +Documentation for LiteX SoC Project +=================================== + + + +Modules +======= + +.. toctree:: + :maxdepth: 1 + + interrupts + +Register Groups +=============== + +.. toctree:: + :maxdepth: 1 + + ctrl + ethmac + ethphy + +Indices and tables +================== + +* :ref:`genindex` +* :ref:`modindex` +* :ref:`search` + diff --git a/gateware/liteeth/doc/interrupts.rst b/gateware/liteeth/doc/interrupts.rst new file mode 100644 index 0000000..9d6df8e --- /dev/null +++ b/gateware/liteeth/doc/interrupts.rst @@ -0,0 +1,18 @@ +Interrupt Controller +==================== + +This device has an ``EventManager``-based interrupt system. Individual modules +generate `events` which are wired into a central interrupt controller. + +When an interrupt occurs, you should look the interrupt number up in the CPU- +specific interrupt table and then call the relevant module. + +Assigned Interrupts +------------------- + +The following interrupts are assigned on this system: + ++-----------+--------+ +| Interrupt | Module | ++===========+========+ + diff --git a/gateware/liteeth/gateware/build_liteeth_core.sh b/gateware/liteeth/gateware/build_liteeth_core.sh new file mode 100644 index 0000000..481970e --- /dev/null +++ b/gateware/liteeth/gateware/build_liteeth_core.sh @@ -0,0 +1,5 @@ +# Autogenerated by LiteX / git: 8159b5ca +set -e +yosys -l liteeth_core.rpt liteeth_core.ys +nextpnr-ecp5 --json liteeth_core.json --lpf liteeth_core.lpf --textcfg liteeth_core.config --45k --package CABGA381 --speed 6 --timing-allow-fail --seed 1 +ecppack --bootaddr 0 --compress liteeth_core.config --svf liteeth_core.svf --bit liteeth_core.bit \ No newline at end of file diff --git a/gateware/liteeth/gateware/liteeth_core.lpf b/gateware/liteeth/gateware/liteeth_core.lpf new file mode 100644 index 0000000..8c2b356 --- /dev/null +++ b/gateware/liteeth/gateware/liteeth_core.lpf @@ -0,0 +1,132 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +LOCATE COMP "sys_clock" SITE "X"; +LOCATE COMP "sys_reset" SITE "X"; +LOCATE COMP "rgmii_eth_clocks_tx" SITE "X"; +LOCATE COMP "rgmii_eth_clocks_rx" SITE "X"; +LOCATE COMP "rgmii_eth_rst_n" SITE "X"; +LOCATE COMP "rgmii_eth_int_n" SITE "X"; +LOCATE COMP "rgmii_eth_mdio" SITE "X"; +LOCATE COMP "rgmii_eth_mdc" SITE "X"; +LOCATE COMP "rgmii_eth_rx_ctl" SITE "X"; +LOCATE COMP "rgmii_eth_rx_data[0]" SITE "X"; +LOCATE COMP "rgmii_eth_rx_data[1]" SITE "X"; +LOCATE COMP "rgmii_eth_rx_data[2]" SITE "X"; +LOCATE COMP "rgmii_eth_rx_data[3]" SITE "X"; +LOCATE COMP "rgmii_eth_tx_ctl" SITE "X"; +LOCATE COMP "rgmii_eth_tx_data[0]" SITE "X"; +LOCATE COMP "rgmii_eth_tx_data[1]" SITE "X"; +LOCATE COMP "rgmii_eth_tx_data[2]" SITE "X"; +LOCATE COMP "rgmii_eth_tx_data[3]" SITE "X"; +LOCATE COMP "wishbone_adr[0]" SITE "X"; +LOCATE COMP "wishbone_adr[1]" SITE "X"; +LOCATE COMP "wishbone_adr[2]" SITE "X"; +LOCATE COMP "wishbone_adr[3]" SITE "X"; +LOCATE COMP "wishbone_adr[4]" SITE "X"; +LOCATE COMP "wishbone_adr[5]" SITE "X"; +LOCATE COMP "wishbone_adr[6]" SITE "X"; +LOCATE COMP "wishbone_adr[7]" SITE "X"; +LOCATE COMP "wishbone_adr[8]" SITE "X"; +LOCATE COMP "wishbone_adr[9]" SITE "X"; +LOCATE COMP "wishbone_adr[10]" SITE "X"; +LOCATE COMP "wishbone_adr[11]" SITE "X"; +LOCATE COMP "wishbone_adr[12]" SITE "X"; +LOCATE COMP "wishbone_adr[13]" SITE "X"; +LOCATE COMP "wishbone_adr[14]" SITE "X"; +LOCATE COMP "wishbone_adr[15]" SITE "X"; +LOCATE COMP "wishbone_adr[16]" SITE "X"; +LOCATE COMP "wishbone_adr[17]" SITE "X"; +LOCATE COMP "wishbone_adr[18]" SITE "X"; +LOCATE COMP "wishbone_adr[19]" SITE "X"; +LOCATE COMP "wishbone_adr[20]" SITE "X"; +LOCATE COMP "wishbone_adr[21]" SITE "X"; +LOCATE COMP "wishbone_adr[22]" SITE "X"; +LOCATE COMP "wishbone_adr[23]" SITE "X"; +LOCATE COMP "wishbone_adr[24]" SITE "X"; +LOCATE COMP "wishbone_adr[25]" SITE "X"; +LOCATE COMP "wishbone_adr[26]" SITE "X"; +LOCATE COMP "wishbone_adr[27]" SITE "X"; +LOCATE COMP "wishbone_adr[28]" SITE "X"; +LOCATE COMP "wishbone_adr[29]" SITE "X"; +LOCATE COMP "wishbone_dat_w[0]" SITE "X"; +LOCATE COMP "wishbone_dat_w[1]" SITE "X"; +LOCATE COMP "wishbone_dat_w[2]" SITE "X"; +LOCATE COMP "wishbone_dat_w[3]" SITE "X"; +LOCATE COMP "wishbone_dat_w[4]" SITE "X"; +LOCATE COMP "wishbone_dat_w[5]" SITE "X"; +LOCATE COMP "wishbone_dat_w[6]" SITE "X"; +LOCATE COMP "wishbone_dat_w[7]" SITE "X"; +LOCATE COMP "wishbone_dat_w[8]" SITE "X"; +LOCATE COMP "wishbone_dat_w[9]" SITE "X"; +LOCATE COMP "wishbone_dat_w[10]" SITE "X"; +LOCATE COMP "wishbone_dat_w[11]" SITE "X"; +LOCATE COMP "wishbone_dat_w[12]" SITE "X"; +LOCATE COMP "wishbone_dat_w[13]" SITE "X"; +LOCATE COMP "wishbone_dat_w[14]" SITE "X"; +LOCATE COMP "wishbone_dat_w[15]" SITE "X"; +LOCATE COMP "wishbone_dat_w[16]" SITE "X"; +LOCATE COMP "wishbone_dat_w[17]" SITE "X"; +LOCATE COMP "wishbone_dat_w[18]" SITE "X"; +LOCATE COMP "wishbone_dat_w[19]" SITE "X"; +LOCATE COMP "wishbone_dat_w[20]" SITE "X"; +LOCATE COMP "wishbone_dat_w[21]" SITE "X"; +LOCATE COMP "wishbone_dat_w[22]" SITE "X"; +LOCATE COMP "wishbone_dat_w[23]" SITE "X"; +LOCATE COMP "wishbone_dat_w[24]" SITE "X"; +LOCATE COMP "wishbone_dat_w[25]" SITE "X"; +LOCATE COMP "wishbone_dat_w[26]" SITE "X"; +LOCATE COMP "wishbone_dat_w[27]" SITE "X"; +LOCATE COMP "wishbone_dat_w[28]" SITE "X"; +LOCATE COMP "wishbone_dat_w[29]" SITE "X"; +LOCATE COMP "wishbone_dat_w[30]" SITE "X"; +LOCATE COMP "wishbone_dat_w[31]" SITE "X"; +LOCATE COMP "wishbone_dat_r[0]" SITE "X"; +LOCATE COMP "wishbone_dat_r[1]" SITE "X"; +LOCATE COMP "wishbone_dat_r[2]" SITE "X"; +LOCATE COMP "wishbone_dat_r[3]" SITE "X"; +LOCATE COMP "wishbone_dat_r[4]" SITE "X"; +LOCATE COMP "wishbone_dat_r[5]" SITE "X"; +LOCATE COMP "wishbone_dat_r[6]" SITE "X"; +LOCATE COMP "wishbone_dat_r[7]" SITE "X"; +LOCATE COMP "wishbone_dat_r[8]" SITE "X"; +LOCATE COMP "wishbone_dat_r[9]" SITE "X"; +LOCATE COMP "wishbone_dat_r[10]" SITE "X"; +LOCATE COMP "wishbone_dat_r[11]" SITE "X"; +LOCATE COMP "wishbone_dat_r[12]" SITE "X"; +LOCATE COMP "wishbone_dat_r[13]" SITE "X"; +LOCATE COMP "wishbone_dat_r[14]" SITE "X"; +LOCATE COMP "wishbone_dat_r[15]" SITE "X"; +LOCATE COMP "wishbone_dat_r[16]" SITE "X"; +LOCATE COMP "wishbone_dat_r[17]" SITE "X"; +LOCATE COMP "wishbone_dat_r[18]" SITE "X"; +LOCATE COMP "wishbone_dat_r[19]" SITE "X"; +LOCATE COMP "wishbone_dat_r[20]" SITE "X"; +LOCATE COMP "wishbone_dat_r[21]" SITE "X"; +LOCATE COMP "wishbone_dat_r[22]" SITE "X"; +LOCATE COMP "wishbone_dat_r[23]" SITE "X"; +LOCATE COMP "wishbone_dat_r[24]" SITE "X"; +LOCATE COMP "wishbone_dat_r[25]" SITE "X"; +LOCATE COMP "wishbone_dat_r[26]" SITE "X"; +LOCATE COMP "wishbone_dat_r[27]" SITE "X"; +LOCATE COMP "wishbone_dat_r[28]" SITE "X"; +LOCATE COMP "wishbone_dat_r[29]" SITE "X"; +LOCATE COMP "wishbone_dat_r[30]" SITE "X"; +LOCATE COMP "wishbone_dat_r[31]" SITE "X"; +LOCATE COMP "wishbone_sel[0]" SITE "X"; +LOCATE COMP "wishbone_sel[1]" SITE "X"; +LOCATE COMP "wishbone_sel[2]" SITE "X"; +LOCATE COMP "wishbone_sel[3]" SITE "X"; +LOCATE COMP "wishbone_cyc" SITE "X"; +LOCATE COMP "wishbone_stb" SITE "X"; +LOCATE COMP "wishbone_ack" SITE "X"; +LOCATE COMP "wishbone_we" SITE "X"; +LOCATE COMP "wishbone_cti[0]" SITE "X"; +LOCATE COMP "wishbone_cti[1]" SITE "X"; +LOCATE COMP "wishbone_cti[2]" SITE "X"; +LOCATE COMP "wishbone_bte[0]" SITE "X"; +LOCATE COMP "wishbone_bte[1]" SITE "X"; +LOCATE COMP "wishbone_err" SITE "X"; +LOCATE COMP "interrupt" SITE "X"; +FREQUENCY PORT "eth_rx_clk" 125.0 MHz; + +FREQUENCY PORT "eth_tx_clk" 125.0 MHz; \ No newline at end of file diff --git a/gateware/liteeth/gateware/liteeth_core.v b/gateware/liteeth/gateware/liteeth_core.v new file mode 100644 index 0000000..75f580b --- /dev/null +++ b/gateware/liteeth/gateware/liteeth_core.v @@ -0,0 +1,3898 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : liteeth_core.v +// Device : LFE5U-45F-6BG381C +// LiteX sha1 : 8159b5ca +// Date : 2023-02-07 21:33:18 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module liteeth_core ( + input wire sys_clock, + input wire sys_reset, + output wire rgmii_eth_clocks_tx, + input wire rgmii_eth_clocks_rx, + output wire rgmii_eth_rst_n, + input wire rgmii_eth_int_n, + input wire rgmii_eth_mdio, + output wire rgmii_eth_mdc, + input wire rgmii_eth_rx_ctl, + input wire [3:0] rgmii_eth_rx_data, + output wire rgmii_eth_tx_ctl, + output wire [3:0] rgmii_eth_tx_data, + input wire [29:0] wishbone_adr, + input wire [31:0] wishbone_dat_w, + output wire [31:0] wishbone_dat_r, + input wire [3:0] wishbone_sel, + input wire wishbone_cyc, + input wire wishbone_stb, + output wire wishbone_ack, + input wire wishbone_we, + input wire [2:0] wishbone_cti, + input wire [1:0] wishbone_bte, + output wire wishbone_err, + output wire interrupt +); + + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +reg main_maccore_maccore_soc_rst = 1'd0; +wire main_maccore_maccore_cpu_rst; +reg [1:0] main_maccore_maccore_reset_storage = 2'd0; +reg main_maccore_maccore_reset_re = 1'd0; +reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; +reg main_maccore_maccore_scratch_re = 1'd0; +wire [31:0] main_maccore_maccore_bus_errors_status; +wire main_maccore_maccore_bus_errors_we; +reg main_maccore_maccore_bus_errors_re = 1'd0; +wire main_maccore_maccore_bus_error; +reg [31:0] main_maccore_maccore_bus_errors = 32'd0; +(* keep = "true" *) wire sys_clk; +wire sys_rst; +wire por_clk; +reg main_maccore_int_rst = 1'd1; +reg main_maccore_ethphy_reset_storage = 1'd0; +reg main_maccore_ethphy_reset_re = 1'd0; +(* keep = "true" *) wire eth_rx_clk; +wire eth_rx_rst; +(* keep = "true" *) wire eth_tx_clk; +wire eth_tx_rst; +wire main_maccore_ethphy_eth_tx_clk_o; +wire main_maccore_ethphy_reset; +wire main_maccore_ethphy_sink_valid; +wire main_maccore_ethphy_sink_ready; +wire main_maccore_ethphy_sink_first; +wire main_maccore_ethphy_sink_last; +wire [7:0] main_maccore_ethphy_sink_payload_data; +wire main_maccore_ethphy_sink_payload_last_be; +wire main_maccore_ethphy_sink_payload_error; +wire main_maccore_ethphy_tx_ctl_oddrx1f; +wire [3:0] main_maccore_ethphy_tx_data_oddrx1f; +reg main_maccore_ethphy_source_valid = 1'd0; +wire main_maccore_ethphy_source_ready; +reg main_maccore_ethphy_source_first = 1'd0; +wire main_maccore_ethphy_source_last; +reg [7:0] main_maccore_ethphy_source_payload_data = 8'd0; +reg main_maccore_ethphy_source_payload_last_be = 1'd0; +reg main_maccore_ethphy_source_payload_error = 1'd0; +reg main_maccore_ethphy_link_status = 1'd0; +reg main_maccore_ethphy_clock_speed = 1'd0; +reg main_maccore_ethphy_duplex_status = 1'd0; +reg [2:0] main_maccore_ethphy_status = 3'd0; +wire main_maccore_ethphy_we; +reg main_maccore_ethphy_re = 1'd0; +wire main_maccore_ethphy_rx_ctl_delayf; +wire [1:0] main_maccore_ethphy_rx_ctl; +reg [1:0] main_maccore_ethphy_rx_ctl_reg = 2'd0; +wire [3:0] main_maccore_ethphy_rx_data_delayf; +wire [7:0] main_maccore_ethphy_rx_data; +reg [7:0] main_maccore_ethphy_rx_data_reg = 8'd0; +reg [1:0] main_maccore_ethphy_rx_ctl_reg_d = 2'd0; +wire main_maccore_ethphy_last; +wire main_maccore_ethphy_mdc; +wire main_maccore_ethphy_oe; +wire main_maccore_ethphy_w; +reg [2:0] main_maccore_ethphy__w_storage = 3'd0; +reg main_maccore_ethphy__w_re = 1'd0; +reg main_maccore_ethphy_r = 1'd0; +reg main_maccore_ethphy__r_status = 1'd0; +wire main_maccore_ethphy__r_we; +reg main_maccore_ethphy__r_re = 1'd0; +wire main_maccore_ethphy_data_w; +wire main_maccore_ethphy_data_oe; +wire main_maccore_ethphy_data_r; +wire main_sink_valid; +wire main_sink_ready; +wire main_sink_first; +wire main_sink_last; +wire [31:0] main_sink_payload_data; +wire [3:0] main_sink_payload_last_be; +wire [3:0] main_sink_payload_error; +wire main_source_valid; +wire main_source_ready; +wire main_source_first; +wire main_source_last; +wire [31:0] main_source_payload_data; +wire [3:0] main_source_payload_last_be; +wire [3:0] main_source_payload_error; +reg main_status = 1'd1; +wire main_we; +reg main_re = 1'd0; +wire main_tx_cdc_sink_sink_valid; +wire main_tx_cdc_sink_sink_ready; +wire main_tx_cdc_sink_sink_first; +wire main_tx_cdc_sink_sink_last; +wire [31:0] main_tx_cdc_sink_sink_payload_data; +wire [3:0] main_tx_cdc_sink_sink_payload_last_be; +wire [3:0] main_tx_cdc_sink_sink_payload_error; +wire main_tx_cdc_source_source_valid; +wire main_tx_cdc_source_source_ready; +wire main_tx_cdc_source_source_first; +wire main_tx_cdc_source_source_last; +wire [31:0] main_tx_cdc_source_source_payload_data; +wire [3:0] main_tx_cdc_source_source_payload_last_be; +wire [3:0] main_tx_cdc_source_source_payload_error; +wire main_tx_cdc_cdc_sink_valid; +wire main_tx_cdc_cdc_sink_ready; +wire main_tx_cdc_cdc_sink_first; +wire main_tx_cdc_cdc_sink_last; +wire [31:0] main_tx_cdc_cdc_sink_payload_data; +wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; +wire [3:0] main_tx_cdc_cdc_sink_payload_error; +wire main_tx_cdc_cdc_source_valid; +wire main_tx_cdc_cdc_source_ready; +wire main_tx_cdc_cdc_source_first; +wire main_tx_cdc_cdc_source_last; +wire [31:0] main_tx_cdc_cdc_source_payload_data; +wire [3:0] main_tx_cdc_cdc_source_payload_last_be; +wire [3:0] main_tx_cdc_cdc_source_payload_error; +wire main_tx_cdc_cdc_asyncfifo_we; +wire main_tx_cdc_cdc_asyncfifo_writable; +wire main_tx_cdc_cdc_asyncfifo_re; +wire main_tx_cdc_cdc_asyncfifo_readable; +wire [41:0] main_tx_cdc_cdc_asyncfifo_din; +wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; +wire main_tx_cdc_cdc_graycounter0_ce; +reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_tx_cdc_cdc_graycounter1_ce; +reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_produce_rdomain; +wire [5:0] main_tx_cdc_cdc_consume_wdomain; +wire [4:0] main_tx_cdc_cdc_wrport_adr; +wire [41:0] main_tx_cdc_cdc_wrport_dat_r; +wire main_tx_cdc_cdc_wrport_we; +wire [41:0] main_tx_cdc_cdc_wrport_dat_w; +wire [4:0] main_tx_cdc_cdc_rdport_adr; +wire [41:0] main_tx_cdc_cdc_rdport_dat_r; +wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; +wire main_tx_cdc_cdc_fifo_in_first; +wire main_tx_cdc_cdc_fifo_in_last; +wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; +wire main_tx_cdc_cdc_fifo_out_first; +wire main_tx_cdc_cdc_fifo_out_last; +wire main_tx_converter_sink_valid; +wire main_tx_converter_sink_ready; +wire main_tx_converter_sink_first; +wire main_tx_converter_sink_last; +wire [31:0] main_tx_converter_sink_payload_data; +wire [3:0] main_tx_converter_sink_payload_last_be; +wire [3:0] main_tx_converter_sink_payload_error; +wire main_tx_converter_source_valid; +wire main_tx_converter_source_ready; +wire main_tx_converter_source_first; +wire main_tx_converter_source_last; +wire [7:0] main_tx_converter_source_payload_data; +wire main_tx_converter_source_payload_last_be; +wire main_tx_converter_source_payload_error; +wire main_tx_converter_converter_sink_valid; +wire main_tx_converter_converter_sink_ready; +wire main_tx_converter_converter_sink_first; +wire main_tx_converter_converter_sink_last; +reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; +wire main_tx_converter_converter_source_valid; +wire main_tx_converter_converter_source_ready; +wire main_tx_converter_converter_source_first; +wire main_tx_converter_converter_source_last; +reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; +wire main_tx_converter_converter_source_payload_valid_token_count; +reg [1:0] main_tx_converter_converter_mux = 2'd0; +wire main_tx_converter_converter_first; +wire main_tx_converter_converter_last; +wire main_tx_converter_source_source_valid; +wire main_tx_converter_source_source_ready; +wire main_tx_converter_source_source_first; +wire main_tx_converter_source_source_last; +wire [9:0] main_tx_converter_source_source_payload_data; +wire main_tx_last_be_sink_valid; +reg main_tx_last_be_sink_ready = 1'd0; +wire main_tx_last_be_sink_first; +wire main_tx_last_be_sink_last; +wire [7:0] main_tx_last_be_sink_payload_data; +wire main_tx_last_be_sink_payload_last_be; +wire main_tx_last_be_sink_payload_error; +reg main_tx_last_be_source_valid = 1'd0; +wire main_tx_last_be_source_ready; +reg main_tx_last_be_source_first = 1'd0; +reg main_tx_last_be_source_last = 1'd0; +reg [7:0] main_tx_last_be_source_payload_data = 8'd0; +reg main_tx_last_be_source_payload_last_be = 1'd0; +reg main_tx_last_be_source_payload_error = 1'd0; +wire main_tx_padding_sink_valid; +reg main_tx_padding_sink_ready = 1'd0; +wire main_tx_padding_sink_first; +wire main_tx_padding_sink_last; +wire [7:0] main_tx_padding_sink_payload_data; +wire main_tx_padding_sink_payload_last_be; +wire main_tx_padding_sink_payload_error; +reg main_tx_padding_source_valid = 1'd0; +wire main_tx_padding_source_ready; +reg main_tx_padding_source_first = 1'd0; +reg main_tx_padding_source_last = 1'd0; +reg [7:0] main_tx_padding_source_payload_data = 8'd0; +reg main_tx_padding_source_payload_last_be = 1'd0; +reg main_tx_padding_source_payload_error = 1'd0; +reg [15:0] main_tx_padding_counter = 16'd0; +wire main_tx_padding_counter_done; +wire main_liteethmaccrc32inserter_sink_valid; +reg main_liteethmaccrc32inserter_sink_ready = 1'd0; +wire main_liteethmaccrc32inserter_sink_first; +wire main_liteethmaccrc32inserter_sink_last; +wire [7:0] main_liteethmaccrc32inserter_sink_payload_data; +wire main_liteethmaccrc32inserter_sink_payload_last_be; +wire main_liteethmaccrc32inserter_sink_payload_error; +reg main_liteethmaccrc32inserter_source_valid = 1'd0; +wire main_liteethmaccrc32inserter_source_ready; +reg main_liteethmaccrc32inserter_source_first = 1'd0; +reg main_liteethmaccrc32inserter_source_last = 1'd0; +reg [7:0] main_liteethmaccrc32inserter_source_payload_data = 8'd0; +reg main_liteethmaccrc32inserter_source_payload_last_be = 1'd0; +reg main_liteethmaccrc32inserter_source_payload_error = 1'd0; +reg [7:0] main_liteethmaccrc32inserter_data0 = 8'd0; +reg main_liteethmaccrc32inserter_last_be0 = 1'd0; +reg [31:0] main_liteethmaccrc32inserter_value = 32'd0; +reg main_liteethmaccrc32inserter_error = 1'd0; +reg main_liteethmaccrc32inserter_last_be1 = 1'd0; +wire [7:0] main_liteethmaccrc32inserter_data1; +wire [31:0] main_liteethmaccrc32inserter_last; +reg [31:0] main_liteethmaccrc32inserter_next = 32'd0; +reg [31:0] main_liteethmaccrc32inserter_reg = 32'd4294967295; +reg main_liteethmaccrc32inserter_ce = 1'd0; +reg main_liteethmaccrc32inserter_reset = 1'd0; +reg [31:0] main_liteethmaccrc32inserter_crc_packet = 32'd0; +reg main_liteethmaccrc32inserter_last_be2 = 1'd0; +reg [1:0] main_liteethmaccrc32inserter_cnt = 2'd3; +wire main_liteethmaccrc32inserter_cnt_done; +reg main_liteethmaccrc32inserter_is_ongoing0 = 1'd0; +reg main_liteethmaccrc32inserter_is_ongoing1 = 1'd0; +wire main_bufferizeendpoints_sink_valid; +wire main_bufferizeendpoints_sink_ready; +wire main_bufferizeendpoints_sink_first; +wire main_bufferizeendpoints_sink_last; +wire [7:0] main_bufferizeendpoints_sink_payload_data; +wire main_bufferizeendpoints_sink_payload_last_be; +wire main_bufferizeendpoints_sink_payload_error; +reg main_bufferizeendpoints_source_valid = 1'd0; +wire main_bufferizeendpoints_source_ready; +reg main_bufferizeendpoints_source_first = 1'd0; +reg main_bufferizeendpoints_source_last = 1'd0; +reg [7:0] main_bufferizeendpoints_source_payload_data = 8'd0; +reg main_bufferizeendpoints_source_payload_last_be = 1'd0; +reg main_bufferizeendpoints_source_payload_error = 1'd0; +wire main_tx_preamble_sink_valid; +reg main_tx_preamble_sink_ready = 1'd0; +wire main_tx_preamble_sink_first; +wire main_tx_preamble_sink_last; +wire [7:0] main_tx_preamble_sink_payload_data; +wire main_tx_preamble_sink_payload_last_be; +wire main_tx_preamble_sink_payload_error; +reg main_tx_preamble_source_valid = 1'd0; +wire main_tx_preamble_source_ready; +reg main_tx_preamble_source_first = 1'd0; +reg main_tx_preamble_source_last = 1'd0; +reg [7:0] main_tx_preamble_source_payload_data = 8'd0; +wire main_tx_preamble_source_payload_last_be; +reg main_tx_preamble_source_payload_error = 1'd0; +reg [63:0] main_tx_preamble_preamble = 64'd15372286728091293013; +reg [2:0] main_tx_preamble_count = 3'd0; +wire main_tx_gap_sink_valid; +reg main_tx_gap_sink_ready = 1'd0; +wire main_tx_gap_sink_first; +wire main_tx_gap_sink_last; +wire [7:0] main_tx_gap_sink_payload_data; +wire main_tx_gap_sink_payload_last_be; +wire main_tx_gap_sink_payload_error; +reg main_tx_gap_source_valid = 1'd0; +wire main_tx_gap_source_ready; +reg main_tx_gap_source_first = 1'd0; +reg main_tx_gap_source_last = 1'd0; +reg [7:0] main_tx_gap_source_payload_data = 8'd0; +reg main_tx_gap_source_payload_last_be = 1'd0; +reg main_tx_gap_source_payload_error = 1'd0; +reg [3:0] main_tx_gap_counter = 4'd0; +reg [31:0] main_preamble_errors_status = 32'd0; +wire main_preamble_errors_we; +reg main_preamble_errors_re = 1'd0; +reg [31:0] main_crc_errors_status = 32'd0; +wire main_crc_errors_we; +reg main_crc_errors_re = 1'd0; +wire main_rx_preamble_sink_valid; +reg main_rx_preamble_sink_ready = 1'd0; +wire main_rx_preamble_sink_first; +wire main_rx_preamble_sink_last; +wire [7:0] main_rx_preamble_sink_payload_data; +wire main_rx_preamble_sink_payload_last_be; +wire main_rx_preamble_sink_payload_error; +reg main_rx_preamble_source_valid = 1'd0; +wire main_rx_preamble_source_ready; +reg main_rx_preamble_source_first = 1'd0; +reg main_rx_preamble_source_last = 1'd0; +wire [7:0] main_rx_preamble_source_payload_data; +wire main_rx_preamble_source_payload_last_be; +reg main_rx_preamble_source_payload_error = 1'd0; +reg main_rx_preamble_error = 1'd0; +reg [63:0] main_rx_preamble_preamble = 64'd15372286728091293013; +wire main_pulsesynchronizer0_i; +wire main_pulsesynchronizer0_o; +reg main_pulsesynchronizer0_toggle_i = 1'd0; +wire main_pulsesynchronizer0_toggle_o; +reg main_pulsesynchronizer0_toggle_o_r = 1'd0; +wire main_rx_crc_sink_sink_valid; +reg main_rx_crc_sink_sink_ready = 1'd0; +wire main_rx_crc_sink_sink_first; +wire main_rx_crc_sink_sink_last; +wire [7:0] main_rx_crc_sink_sink_payload_data; +wire main_rx_crc_sink_sink_payload_last_be; +wire main_rx_crc_sink_sink_payload_error; +reg main_rx_crc_source_source_valid = 1'd0; +wire main_rx_crc_source_source_ready; +reg main_rx_crc_source_source_first = 1'd0; +reg main_rx_crc_source_source_last = 1'd0; +reg [7:0] main_rx_crc_source_source_payload_data = 8'd0; +reg main_rx_crc_source_source_payload_last_be = 1'd0; +reg main_rx_crc_source_source_payload_error = 1'd0; +reg main_rx_crc_error = 1'd0; +wire [7:0] main_rx_crc_crc_data0; +wire main_rx_crc_crc_last_be0; +reg [31:0] main_rx_crc_crc_value = 32'd0; +reg main_rx_crc_crc_error0 = 1'd0; +reg main_rx_crc_crc_last_be1 = 1'd0; +wire [7:0] main_rx_crc_crc_data1; +wire [31:0] main_rx_crc_crc_last; +reg [31:0] main_rx_crc_crc_next = 32'd0; +reg [31:0] main_rx_crc_crc_reg = 32'd4294967295; +reg main_rx_crc_crc_ce = 1'd0; +reg main_rx_crc_crc_reset = 1'd0; +reg main_rx_crc_syncfifo_sink_valid = 1'd0; +wire main_rx_crc_syncfifo_sink_ready; +wire main_rx_crc_syncfifo_sink_first; +wire main_rx_crc_syncfifo_sink_last; +wire [7:0] main_rx_crc_syncfifo_sink_payload_data; +wire main_rx_crc_syncfifo_sink_payload_last_be; +wire main_rx_crc_syncfifo_sink_payload_error; +wire main_rx_crc_syncfifo_source_valid; +reg main_rx_crc_syncfifo_source_ready = 1'd0; +wire main_rx_crc_syncfifo_source_first; +wire main_rx_crc_syncfifo_source_last; +wire [7:0] main_rx_crc_syncfifo_source_payload_data; +wire main_rx_crc_syncfifo_source_payload_last_be; +wire main_rx_crc_syncfifo_source_payload_error; +wire main_rx_crc_syncfifo_syncfifo_we; +wire main_rx_crc_syncfifo_syncfifo_writable; +wire main_rx_crc_syncfifo_syncfifo_re; +wire main_rx_crc_syncfifo_syncfifo_readable; +wire [11:0] main_rx_crc_syncfifo_syncfifo_din; +wire [11:0] main_rx_crc_syncfifo_syncfifo_dout; +reg [2:0] main_rx_crc_syncfifo_level = 3'd0; +reg main_rx_crc_syncfifo_replace = 1'd0; +reg [2:0] main_rx_crc_syncfifo_produce = 3'd0; +reg [2:0] main_rx_crc_syncfifo_consume = 3'd0; +reg [2:0] main_rx_crc_syncfifo_wrport_adr = 3'd0; +wire [11:0] main_rx_crc_syncfifo_wrport_dat_r; +wire main_rx_crc_syncfifo_wrport_we; +wire [11:0] main_rx_crc_syncfifo_wrport_dat_w; +wire main_rx_crc_syncfifo_do_read; +wire [2:0] main_rx_crc_syncfifo_rdport_adr; +wire [11:0] main_rx_crc_syncfifo_rdport_dat_r; +wire [7:0] main_rx_crc_syncfifo_fifo_in_payload_data; +wire main_rx_crc_syncfifo_fifo_in_payload_last_be; +wire main_rx_crc_syncfifo_fifo_in_payload_error; +wire main_rx_crc_syncfifo_fifo_in_first; +wire main_rx_crc_syncfifo_fifo_in_last; +wire [7:0] main_rx_crc_syncfifo_fifo_out_payload_data; +wire main_rx_crc_syncfifo_fifo_out_payload_last_be; +wire main_rx_crc_syncfifo_fifo_out_payload_error; +wire main_rx_crc_syncfifo_fifo_out_first; +wire main_rx_crc_syncfifo_fifo_out_last; +reg main_rx_crc_fifo_reset = 1'd0; +wire main_rx_crc_fifo_in; +wire main_rx_crc_fifo_out; +wire main_rx_crc_fifo_full; +reg main_rx_crc_last_be = 1'd0; +reg main_rx_crc_crc_error1 = 1'd0; +wire main_rx_crc_sink_valid; +wire main_rx_crc_sink_ready; +wire main_rx_crc_sink_first; +wire main_rx_crc_sink_last; +wire [7:0] main_rx_crc_sink_payload_data; +wire main_rx_crc_sink_payload_last_be; +wire main_rx_crc_sink_payload_error; +reg main_rx_crc_source_valid = 1'd0; +wire main_rx_crc_source_ready; +reg main_rx_crc_source_first = 1'd0; +reg main_rx_crc_source_last = 1'd0; +reg [7:0] main_rx_crc_source_payload_data = 8'd0; +reg main_rx_crc_source_payload_last_be = 1'd0; +reg main_rx_crc_source_payload_error = 1'd0; +wire main_pulsesynchronizer1_i; +wire main_pulsesynchronizer1_o; +reg main_pulsesynchronizer1_toggle_i = 1'd0; +wire main_pulsesynchronizer1_toggle_o; +reg main_pulsesynchronizer1_toggle_o_r = 1'd0; +wire main_rx_padding_sink_valid; +wire main_rx_padding_sink_ready; +wire main_rx_padding_sink_first; +wire main_rx_padding_sink_last; +wire [7:0] main_rx_padding_sink_payload_data; +wire main_rx_padding_sink_payload_last_be; +wire main_rx_padding_sink_payload_error; +wire main_rx_padding_source_valid; +wire main_rx_padding_source_ready; +wire main_rx_padding_source_first; +wire main_rx_padding_source_last; +wire [7:0] main_rx_padding_source_payload_data; +wire main_rx_padding_source_payload_last_be; +wire main_rx_padding_source_payload_error; +wire main_rx_last_be_sink_valid; +wire main_rx_last_be_sink_ready; +wire main_rx_last_be_sink_first; +wire main_rx_last_be_sink_last; +wire [7:0] main_rx_last_be_sink_payload_data; +wire main_rx_last_be_sink_payload_last_be; +wire main_rx_last_be_sink_payload_error; +wire main_rx_last_be_source_valid; +wire main_rx_last_be_source_ready; +wire main_rx_last_be_source_first; +wire main_rx_last_be_source_last; +wire [7:0] main_rx_last_be_source_payload_data; +reg main_rx_last_be_source_payload_last_be = 1'd0; +wire main_rx_last_be_source_payload_error; +wire main_rx_converter_sink_valid; +wire main_rx_converter_sink_ready; +wire main_rx_converter_sink_first; +wire main_rx_converter_sink_last; +wire [7:0] main_rx_converter_sink_payload_data; +wire main_rx_converter_sink_payload_last_be; +wire main_rx_converter_sink_payload_error; +wire main_rx_converter_source_valid; +wire main_rx_converter_source_ready; +wire main_rx_converter_source_first; +wire main_rx_converter_source_last; +reg [31:0] main_rx_converter_source_payload_data = 32'd0; +reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; +reg [3:0] main_rx_converter_source_payload_error = 4'd0; +wire main_rx_converter_converter_sink_valid; +wire main_rx_converter_converter_sink_ready; +wire main_rx_converter_converter_sink_first; +wire main_rx_converter_converter_sink_last; +wire [9:0] main_rx_converter_converter_sink_payload_data; +wire main_rx_converter_converter_source_valid; +wire main_rx_converter_converter_source_ready; +reg main_rx_converter_converter_source_first = 1'd0; +reg main_rx_converter_converter_source_last = 1'd0; +reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; +reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; +reg [1:0] main_rx_converter_converter_demux = 2'd0; +wire main_rx_converter_converter_load_part; +reg main_rx_converter_converter_strobe_all = 1'd0; +wire main_rx_converter_source_source_valid; +wire main_rx_converter_source_source_ready; +wire main_rx_converter_source_source_first; +wire main_rx_converter_source_source_last; +wire [39:0] main_rx_converter_source_source_payload_data; +wire main_rx_cdc_sink_sink_valid; +wire main_rx_cdc_sink_sink_ready; +wire main_rx_cdc_sink_sink_first; +wire main_rx_cdc_sink_sink_last; +wire [31:0] main_rx_cdc_sink_sink_payload_data; +wire [3:0] main_rx_cdc_sink_sink_payload_last_be; +wire [3:0] main_rx_cdc_sink_sink_payload_error; +wire main_rx_cdc_source_source_valid; +wire main_rx_cdc_source_source_ready; +wire main_rx_cdc_source_source_first; +wire main_rx_cdc_source_source_last; +wire [31:0] main_rx_cdc_source_source_payload_data; +wire [3:0] main_rx_cdc_source_source_payload_last_be; +wire [3:0] main_rx_cdc_source_source_payload_error; +wire main_rx_cdc_cdc_sink_valid; +wire main_rx_cdc_cdc_sink_ready; +wire main_rx_cdc_cdc_sink_first; +wire main_rx_cdc_cdc_sink_last; +wire [31:0] main_rx_cdc_cdc_sink_payload_data; +wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; +wire [3:0] main_rx_cdc_cdc_sink_payload_error; +wire main_rx_cdc_cdc_source_valid; +wire main_rx_cdc_cdc_source_ready; +wire main_rx_cdc_cdc_source_first; +wire main_rx_cdc_cdc_source_last; +wire [31:0] main_rx_cdc_cdc_source_payload_data; +wire [3:0] main_rx_cdc_cdc_source_payload_last_be; +wire [3:0] main_rx_cdc_cdc_source_payload_error; +wire main_rx_cdc_cdc_asyncfifo_we; +wire main_rx_cdc_cdc_asyncfifo_writable; +wire main_rx_cdc_cdc_asyncfifo_re; +wire main_rx_cdc_cdc_asyncfifo_readable; +wire [41:0] main_rx_cdc_cdc_asyncfifo_din; +wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; +wire main_rx_cdc_cdc_graycounter0_ce; +reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_rx_cdc_cdc_graycounter1_ce; +reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_produce_rdomain; +wire [5:0] main_rx_cdc_cdc_consume_wdomain; +wire [4:0] main_rx_cdc_cdc_wrport_adr; +wire [41:0] main_rx_cdc_cdc_wrport_dat_r; +wire main_rx_cdc_cdc_wrport_we; +wire [41:0] main_rx_cdc_cdc_wrport_dat_w; +wire [4:0] main_rx_cdc_cdc_rdport_adr; +wire [41:0] main_rx_cdc_cdc_rdport_dat_r; +wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; +wire main_rx_cdc_cdc_fifo_in_first; +wire main_rx_cdc_cdc_fifo_in_last; +wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; +wire main_rx_cdc_cdc_fifo_out_first; +wire main_rx_cdc_cdc_fifo_out_last; +wire main_sink_sink_valid; +wire main_sink_sink_ready; +wire main_sink_sink_first; +wire main_sink_sink_last; +wire [31:0] main_sink_sink_payload_data; +wire [3:0] main_sink_sink_payload_last_be; +wire [3:0] main_sink_sink_payload_error; +wire main_source_source_valid; +wire main_source_source_ready; +wire main_source_source_first; +wire main_source_source_last; +wire [31:0] main_source_source_payload_data; +wire [3:0] main_source_source_payload_last_be; +wire [3:0] main_source_source_payload_error; +wire [29:0] main_bus_adr; +wire [31:0] main_bus_dat_w; +wire [31:0] main_bus_dat_r; +wire [3:0] main_bus_sel; +wire main_bus_cyc; +wire main_bus_stb; +wire main_bus_ack; +wire main_bus_we; +wire [2:0] main_bus_cti; +wire [1:0] main_bus_bte; +wire main_bus_err; +wire main_sram0_sink_valid; +reg main_sram1_sink_ready = 1'd1; +wire main_sram2_sink_first; +wire main_sram3_sink_last; +wire [31:0] main_sram4_sink_payload_data; +wire [3:0] main_sram5_sink_payload_last_be; +wire [3:0] main_sram6_sink_payload_error; +wire main_sram7_status; +wire main_sram8_we; +reg main_sram9_re = 1'd0; +wire [10:0] main_sram10_status; +wire main_sram11_we; +reg main_sram12_re = 1'd0; +reg [31:0] main_sram13_status = 32'd0; +wire main_sram14_we; +reg main_sram15_re = 1'd0; +wire main_sram16_irq; +wire main_sram17_status; +wire main_sram18_pending; +wire main_sram19_trigger; +reg main_sram20_clear = 1'd0; +wire main_sram21_available; +wire main_sram22_status; +wire main_sram23_we; +reg main_sram24_re = 1'd0; +wire main_sram25_available; +wire main_sram26_status; +wire main_sram27_we; +reg main_sram28_re = 1'd0; +reg main_sram29_r = 1'd0; +wire main_sram30_available; +reg main_sram31_storage = 1'd0; +reg main_sram32_re = 1'd0; +reg main_write = 1'd0; +reg main_slot = 1'd0; +reg [10:0] main_sram35_length = 11'd0; +reg [3:0] main_length_inc = 4'd0; +reg main_sram37_sink_valid = 1'd0; +wire main_sram38_sink_ready; +reg main_sram39_sink_first = 1'd0; +reg main_sram40_sink_last = 1'd0; +reg main_sram41_sink_payload_slot = 1'd0; +reg [10:0] main_sram42_sink_payload_length = 11'd0; +wire main_sram43_source_valid; +wire main_sram44_source_ready; +wire main_sram45_source_first; +wire main_sram46_source_last; +wire main_sram47_source_payload_slot; +wire [10:0] main_sram48_source_payload_length; +wire main_sram49_we; +wire main_sram50_writable; +wire main_sram51_re; +wire main_sram52_readable; +wire [13:0] main_sram53_din; +wire [13:0] main_sram54_dout; +reg [1:0] main_sram55_level = 2'd0; +reg main_sram56_replace = 1'd0; +reg main_sram57_produce = 1'd0; +reg main_sram58_consume = 1'd0; +reg main_sram59_adr = 1'd0; +wire [13:0] main_sram60_dat_r; +wire main_sram61_we; +wire [13:0] main_sram62_dat_w; +wire main_sram63_do_read; +wire main_sram64_adr; +wire [13:0] main_sram65_dat_r; +wire main_sram66_fifo_in_payload_slot; +wire [10:0] main_sram67_fifo_in_payload_length; +wire main_sram68_fifo_in_first; +wire main_sram69_fifo_in_last; +wire main_sram70_fifo_out_payload_slot; +wire [10:0] main_sram71_fifo_out_payload_length; +wire main_sram72_fifo_out_first; +wire main_sram73_fifo_out_last; +wire [31:0] main_wr_data; +reg [8:0] main_sram75_adr = 9'd0; +wire [31:0] main_sram76_dat_r; +reg main_sram77_we = 1'd0; +reg [31:0] main_sram78_dat_w = 32'd0; +reg [8:0] main_sram79_adr = 9'd0; +wire [31:0] main_sram80_dat_r; +reg main_sram81_we = 1'd0; +reg [31:0] main_sram82_dat_w = 32'd0; +reg main_sram83_source_valid = 1'd0; +wire main_sram84_source_ready; +reg main_sram85_source_first = 1'd0; +reg main_sram86_source_last = 1'd0; +wire [31:0] main_sram87_source_payload_data; +reg [3:0] main_sram88_source_payload_last_be = 4'd0; +reg [3:0] main_sram89_source_payload_error = 4'd0; +reg main_start_re = 1'd0; +wire main_start_r; +reg main_start_we = 1'd0; +reg main_start_w = 1'd0; +wire main_sram94_status; +wire main_sram95_we; +reg main_sram96_re = 1'd0; +wire [1:0] main_sram97_status; +wire main_sram98_we; +reg main_sram99_re = 1'd0; +reg main_sram100_storage = 1'd0; +reg main_sram101_re = 1'd0; +reg [10:0] main_sram102_storage = 11'd0; +reg main_sram103_re = 1'd0; +wire main_sram104_irq; +wire main_sram105_status; +reg main_sram106_pending = 1'd0; +reg main_sram107_trigger = 1'd0; +reg main_sram108_clear = 1'd0; +wire main_sram109_event0; +wire main_sram110_status; +wire main_sram111_we; +reg main_sram112_re = 1'd0; +wire main_sram113_event0; +wire main_sram114_status; +wire main_sram115_we; +reg main_sram116_re = 1'd0; +reg main_sram117_r = 1'd0; +wire main_sram118_event0; +reg main_sram119_storage = 1'd0; +reg main_sram120_re = 1'd0; +reg main_read = 1'd0; +reg [10:0] main_sram122_length = 11'd0; +wire main_sram123_sink_valid; +wire main_sram124_sink_ready; +reg main_sram125_sink_first = 1'd0; +reg main_sram126_sink_last = 1'd0; +wire main_sram127_sink_payload_slot; +wire [10:0] main_sram128_sink_payload_length; +wire main_sram129_source_valid; +reg main_sram130_source_ready = 1'd0; +wire main_sram131_source_first; +wire main_sram132_source_last; +wire main_sram133_source_payload_slot; +wire [10:0] main_sram134_source_payload_length; +wire main_sram135_we; +wire main_sram136_writable; +wire main_sram137_re; +wire main_sram138_readable; +wire [13:0] main_sram139_din; +wire [13:0] main_sram140_dout; +reg [1:0] main_sram141_level = 2'd0; +reg main_sram142_replace = 1'd0; +reg main_sram143_produce = 1'd0; +reg main_sram144_consume = 1'd0; +reg main_sram145_adr = 1'd0; +wire [13:0] main_sram146_dat_r; +wire main_sram147_we; +wire [13:0] main_sram148_dat_w; +wire main_sram149_do_read; +wire main_sram150_adr; +wire [13:0] main_sram151_dat_r; +wire main_sram152_fifo_in_payload_slot; +wire [10:0] main_sram153_fifo_in_payload_length; +wire main_sram154_fifo_in_first; +wire main_sram155_fifo_in_last; +wire main_sram156_fifo_out_payload_slot; +wire [10:0] main_sram157_fifo_out_payload_length; +wire main_sram158_fifo_out_first; +wire main_sram159_fifo_out_last; +reg [31:0] main_rd_data = 32'd0; +wire [8:0] main_sram161_adr; +wire [31:0] main_sram162_dat_r; +wire main_sram163_re; +wire [8:0] main_sram164_adr; +wire [31:0] main_sram165_dat_r; +wire main_sram166_re; +wire main_sram167_irq; +wire [29:0] main_interface0_adr; +wire [31:0] main_interface0_dat_w; +wire [31:0] main_interface0_dat_r; +wire [3:0] main_interface0_sel; +wire main_interface0_cyc; +wire main_interface0_stb; +reg main_interface0_ack = 1'd0; +wire main_interface0_we; +wire [2:0] main_interface0_cti; +wire [1:0] main_interface0_bte; +reg main_interface0_err = 1'd0; +reg main_sram0_adr_burst = 1'd0; +wire [8:0] main_sram0_adr; +wire [31:0] main_sram0_dat_r; +wire [29:0] main_interface1_adr; +wire [31:0] main_interface1_dat_w; +wire [31:0] main_interface1_dat_r; +wire [3:0] main_interface1_sel; +wire main_interface1_cyc; +wire main_interface1_stb; +reg main_interface1_ack = 1'd0; +wire main_interface1_we; +wire [2:0] main_interface1_cti; +wire [1:0] main_interface1_bte; +reg main_interface1_err = 1'd0; +reg main_sram1_adr_burst = 1'd0; +wire [8:0] main_sram1_adr; +wire [31:0] main_sram1_dat_r; +wire [29:0] main_interface2_adr; +wire [31:0] main_interface2_dat_w; +wire [31:0] main_interface2_dat_r; +wire [3:0] main_interface2_sel; +wire main_interface2_cyc; +wire main_interface2_stb; +reg main_interface2_ack = 1'd0; +wire main_interface2_we; +wire [2:0] main_interface2_cti; +wire [1:0] main_interface2_bte; +reg main_interface2_err = 1'd0; +reg main_sram2_adr_burst = 1'd0; +wire [8:0] main_sram2_adr; +wire [31:0] main_sram2_dat_r; +reg [3:0] main_sram2_we = 4'd0; +wire [31:0] main_sram2_dat_w; +wire [29:0] main_interface3_adr; +wire [31:0] main_interface3_dat_w; +wire [31:0] main_interface3_dat_r; +wire [3:0] main_interface3_sel; +wire main_interface3_cyc; +wire main_interface3_stb; +reg main_interface3_ack = 1'd0; +wire main_interface3_we; +wire [2:0] main_interface3_cti; +wire [1:0] main_interface3_bte; +reg main_interface3_err = 1'd0; +reg main_sram3_adr_burst = 1'd0; +wire [8:0] main_sram3_adr; +wire [31:0] main_sram3_dat_r; +reg [3:0] main_sram3_we = 4'd0; +wire [31:0] main_sram3_dat_w; +reg [3:0] main_slave_sel = 4'd0; +reg [3:0] main_slave_sel_r = 4'd0; +wire [29:0] main_wb_bus_adr; +wire [31:0] main_wb_bus_dat_w; +wire [31:0] main_wb_bus_dat_r; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_cyc; +wire main_wb_bus_stb; +wire main_wb_bus_ack; +wire main_wb_bus_we; +wire [2:0] main_wb_bus_cti; +wire [1:0] main_wb_bus_bte; +wire main_wb_bus_err; +reg [13:0] builder_maccore_adr = 14'd0; +reg builder_maccore_we = 1'd0; +reg [31:0] builder_maccore_dat_w = 32'd0; +wire [31:0] builder_maccore_dat_r; +wire [29:0] builder_maccore_wishbone_adr; +wire [31:0] builder_maccore_wishbone_dat_w; +reg [31:0] builder_maccore_wishbone_dat_r = 32'd0; +wire [3:0] builder_maccore_wishbone_sel; +wire builder_maccore_wishbone_cyc; +wire builder_maccore_wishbone_stb; +reg builder_maccore_wishbone_ack = 1'd0; +wire builder_maccore_wishbone_we; +wire [2:0] builder_maccore_wishbone_cti; +wire [1:0] builder_maccore_wishbone_bte; +reg builder_maccore_wishbone_err = 1'd0; +wire [29:0] builder_shared_adr; +wire [31:0] builder_shared_dat_w; +reg [31:0] builder_shared_dat_r = 32'd0; +wire [3:0] builder_shared_sel; +wire builder_shared_cyc; +wire builder_shared_stb; +reg builder_shared_ack = 1'd0; +wire builder_shared_we; +wire [2:0] builder_shared_cti; +wire [1:0] builder_shared_bte; +wire builder_shared_err; +wire builder_request; +wire builder_grant; +reg [1:0] builder_slave_sel = 2'd0; +reg [1:0] builder_slave_sel_r = 2'd0; +reg builder_error = 1'd0; +wire builder_wait; +wire builder_done; +reg [19:0] builder_count = 20'd1000000; +wire [13:0] builder_interface0_bank_bus_adr; +wire builder_interface0_bank_bus_we; +wire [31:0] builder_interface0_bank_bus_dat_w; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +reg builder_csrbank0_reset0_re = 1'd0; +wire [1:0] builder_csrbank0_reset0_r; +reg builder_csrbank0_reset0_we = 1'd0; +wire [1:0] builder_csrbank0_reset0_w; +reg builder_csrbank0_scratch0_re = 1'd0; +wire [31:0] builder_csrbank0_scratch0_r; +reg builder_csrbank0_scratch0_we = 1'd0; +wire [31:0] builder_csrbank0_scratch0_w; +reg builder_csrbank0_bus_errors_re = 1'd0; +wire [31:0] builder_csrbank0_bus_errors_r; +reg builder_csrbank0_bus_errors_we = 1'd0; +wire [31:0] builder_csrbank0_bus_errors_w; +wire builder_csrbank0_sel; +wire [13:0] builder_interface1_bank_bus_adr; +wire builder_interface1_bank_bus_we; +wire [31:0] builder_interface1_bank_bus_dat_w; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +reg builder_csrbank1_sram_writer_slot_re = 1'd0; +wire builder_csrbank1_sram_writer_slot_r; +reg builder_csrbank1_sram_writer_slot_we = 1'd0; +wire builder_csrbank1_sram_writer_slot_w; +reg builder_csrbank1_sram_writer_length_re = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_r; +reg builder_csrbank1_sram_writer_length_we = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_w; +reg builder_csrbank1_sram_writer_errors_re = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_r; +reg builder_csrbank1_sram_writer_errors_we = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_w; +reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_r; +reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_w; +reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_r; +reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_w; +reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_r; +reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_w; +reg builder_csrbank1_sram_reader_ready_re = 1'd0; +wire builder_csrbank1_sram_reader_ready_r; +reg builder_csrbank1_sram_reader_ready_we = 1'd0; +wire builder_csrbank1_sram_reader_ready_w; +reg builder_csrbank1_sram_reader_level_re = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_r; +reg builder_csrbank1_sram_reader_level_we = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_w; +reg builder_csrbank1_sram_reader_slot0_re = 1'd0; +wire builder_csrbank1_sram_reader_slot0_r; +reg builder_csrbank1_sram_reader_slot0_we = 1'd0; +wire builder_csrbank1_sram_reader_slot0_w; +reg builder_csrbank1_sram_reader_length0_re = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_r; +reg builder_csrbank1_sram_reader_length0_we = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_w; +reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_r; +reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_w; +reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_r; +reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_w; +reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_enable0_r; +reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_enable0_w; +reg builder_csrbank1_preamble_crc_re = 1'd0; +wire builder_csrbank1_preamble_crc_r; +reg builder_csrbank1_preamble_crc_we = 1'd0; +wire builder_csrbank1_preamble_crc_w; +reg builder_csrbank1_rx_datapath_preamble_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_r; +reg builder_csrbank1_rx_datapath_preamble_errors_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_w; +reg builder_csrbank1_rx_datapath_crc_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_r; +reg builder_csrbank1_rx_datapath_crc_errors_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_w; +wire builder_csrbank1_sel; +wire [13:0] builder_interface2_bank_bus_adr; +wire builder_interface2_bank_bus_we; +wire [31:0] builder_interface2_bank_bus_dat_w; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +reg builder_csrbank2_crg_reset0_re = 1'd0; +wire builder_csrbank2_crg_reset0_r; +reg builder_csrbank2_crg_reset0_we = 1'd0; +wire builder_csrbank2_crg_reset0_w; +reg builder_csrbank2_rx_inband_status_re = 1'd0; +wire [2:0] builder_csrbank2_rx_inband_status_r; +reg builder_csrbank2_rx_inband_status_we = 1'd0; +wire [2:0] builder_csrbank2_rx_inband_status_w; +reg builder_csrbank2_mdio_w0_re = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_r; +reg builder_csrbank2_mdio_w0_we = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_w; +reg builder_csrbank2_mdio_r_re = 1'd0; +wire builder_csrbank2_mdio_r_r; +reg builder_csrbank2_mdio_r_we = 1'd0; +wire builder_csrbank2_mdio_r_w; +wire builder_csrbank2_sel; +wire [13:0] builder_csr_interconnect_adr; +wire builder_csr_interconnect_we; +wire [31:0] builder_csr_interconnect_dat_w; +wire [31:0] builder_csr_interconnect_dat_r; +reg builder_maccore_txdatapath_liteethmactxlastbe_state = 1'd0; +reg builder_maccore_txdatapath_liteethmactxlastbe_next_state = 1'd0; +reg builder_maccore_txdatapath_liteethmacpaddinginserter_state = 1'd0; +reg builder_maccore_txdatapath_liteethmacpaddinginserter_next_state = 1'd0; +reg [15:0] main_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; +reg main_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; +reg [1:0] builder_maccore_txdatapath_bufferizeendpoints_state = 2'd0; +reg [1:0] builder_maccore_txdatapath_bufferizeendpoints_next_state = 2'd0; +reg [31:0] main_liteethmaccrc32inserter_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; +reg main_liteethmaccrc32inserter_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; +reg main_liteethmaccrc32inserter_last_be2_clockdomainsrenamer1_next_value1 = 1'd0; +reg main_liteethmaccrc32inserter_last_be2_clockdomainsrenamer1_next_value_ce1 = 1'd0; +reg [1:0] builder_maccore_txdatapath_liteethmacpreambleinserter_state = 2'd0; +reg [1:0] builder_maccore_txdatapath_liteethmacpreambleinserter_next_state = 2'd0; +reg [2:0] main_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; +reg main_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; +reg builder_maccore_txdatapath_liteethmacgap_state = 1'd0; +reg builder_maccore_txdatapath_liteethmacgap_next_state = 1'd0; +reg [3:0] main_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; +reg main_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; +reg builder_maccore_rxdatapath_liteethmacpreamblechecker_state = 1'd0; +reg builder_maccore_rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; +reg [1:0] builder_maccore_rxdatapath_bufferizeendpoints_state = 2'd0; +reg [1:0] builder_maccore_rxdatapath_bufferizeendpoints_next_state = 2'd0; +reg main_rx_crc_last_be_next_value0 = 1'd0; +reg main_rx_crc_last_be_next_value_ce0 = 1'd0; +reg main_rx_crc_crc_error1_next_value1 = 1'd0; +reg main_rx_crc_crc_error1_next_value_ce1 = 1'd0; +reg [1:0] builder_maccore_liteethmacsramwriter_state = 2'd0; +reg [1:0] builder_maccore_liteethmacsramwriter_next_state = 2'd0; +reg [10:0] main_sram35_length_liteethmacsramwriter_t_next_value = 11'd0; +reg main_sram35_length_liteethmacsramwriter_t_next_value_ce = 1'd0; +reg [31:0] main_sram13_status_liteethmacsramwriter_f_next_value = 32'd0; +reg main_sram13_status_liteethmacsramwriter_f_next_value_ce = 1'd0; +reg main_slot_liteethmacsramwriter_next_value = 1'd0; +reg main_slot_liteethmacsramwriter_next_value_ce = 1'd0; +reg [1:0] builder_maccore_liteethmacsramreader_state = 2'd0; +reg [1:0] builder_maccore_liteethmacsramreader_next_state = 2'd0; +reg [10:0] main_sram122_length_liteethmacsramreader_next_value = 11'd0; +reg main_sram122_length_liteethmacsramreader_next_value_ce = 1'd0; +reg builder_maccore_state = 1'd0; +reg builder_maccore_next_state = 1'd0; +wire [31:0] builder_t_slice_proxy0; +wire [31:0] builder_t_slice_proxy1; +wire [31:0] builder_t_slice_proxy2; +wire [31:0] builder_t_slice_proxy3; +wire [31:0] builder_t_slice_proxy4; +wire [31:0] builder_t_slice_proxy5; +wire [31:0] builder_t_slice_proxy6; +wire [31:0] builder_t_slice_proxy7; +wire [31:0] builder_t_slice_proxy8; +wire [31:0] builder_t_slice_proxy9; +wire [31:0] builder_t_slice_proxy10; +wire [31:0] builder_t_slice_proxy11; +wire [31:0] builder_t_slice_proxy12; +wire [31:0] builder_t_slice_proxy13; +wire [31:0] builder_t_slice_proxy14; +wire [31:0] builder_t_slice_proxy15; +wire [31:0] builder_t_slice_proxy16; +wire [31:0] builder_t_slice_proxy17; +wire [31:0] builder_t_slice_proxy18; +wire [31:0] builder_t_slice_proxy19; +wire [31:0] builder_t_slice_proxy20; +wire [31:0] builder_t_slice_proxy21; +wire [31:0] builder_t_slice_proxy22; +wire [31:0] builder_t_slice_proxy23; +wire [31:0] builder_t_slice_proxy24; +wire [31:0] builder_t_slice_proxy25; +wire [31:0] builder_t_slice_proxy26; +wire [31:0] builder_t_slice_proxy27; +wire [31:0] builder_t_slice_proxy28; +wire [31:0] builder_t_slice_proxy29; +wire [31:0] builder_t_slice_proxy30; +wire [31:0] builder_t_slice_proxy31; +wire [39:0] builder_cases_slice_proxy; +wire [31:0] builder_t_slice_proxy32; +wire [31:0] builder_t_slice_proxy33; +wire [31:0] builder_t_slice_proxy34; +wire [31:0] builder_t_slice_proxy35; +wire [31:0] builder_t_slice_proxy36; +wire [31:0] builder_t_slice_proxy37; +wire [31:0] builder_t_slice_proxy38; +wire [31:0] builder_t_slice_proxy39; +wire [31:0] builder_t_slice_proxy40; +wire [31:0] builder_t_slice_proxy41; +wire [31:0] builder_t_slice_proxy42; +wire [31:0] builder_t_slice_proxy43; +wire [31:0] builder_t_slice_proxy44; +wire [31:0] builder_t_slice_proxy45; +wire [31:0] builder_t_slice_proxy46; +wire [31:0] builder_t_slice_proxy47; +wire [31:0] builder_t_slice_proxy48; +wire [31:0] builder_t_slice_proxy49; +wire [31:0] builder_t_slice_proxy50; +wire [31:0] builder_t_slice_proxy51; +wire [31:0] builder_t_slice_proxy52; +wire [31:0] builder_t_slice_proxy53; +wire [31:0] builder_t_slice_proxy54; +wire [31:0] builder_t_slice_proxy55; +wire [31:0] builder_t_slice_proxy56; +wire [31:0] builder_t_slice_proxy57; +wire [31:0] builder_t_slice_proxy58; +wire [31:0] builder_t_slice_proxy59; +wire [31:0] builder_t_slice_proxy60; +wire [31:0] builder_t_slice_proxy61; +wire [31:0] builder_t_slice_proxy62; +wire [31:0] builder_t_slice_proxy63; +reg [29:0] builder_array_muxed0 = 30'd0; +reg [31:0] builder_array_muxed1 = 32'd0; +reg [3:0] builder_array_muxed2 = 4'd0; +reg builder_array_muxed3 = 1'd0; +reg builder_array_muxed4 = 1'd0; +reg builder_array_muxed5 = 1'd0; +reg [2:0] builder_array_muxed6 = 3'd0; +reg [1:0] builder_array_muxed7 = 2'd0; +wire builder_rst10; +wire builder_rst11; +reg builder_multiregimpl0_regs0 = 1'd0; +reg builder_multiregimpl0_regs1 = 1'd0; +reg [5:0] builder_multiregimpl1_regs0 = 6'd0; +reg [5:0] builder_multiregimpl1_regs1 = 6'd0; +reg [5:0] builder_multiregimpl2_regs0 = 6'd0; +reg [5:0] builder_multiregimpl2_regs1 = 6'd0; +reg builder_multiregimpl3_regs0 = 1'd0; +reg builder_multiregimpl3_regs1 = 1'd0; +reg builder_multiregimpl4_regs0 = 1'd0; +reg builder_multiregimpl4_regs1 = 1'd0; +reg [5:0] builder_multiregimpl5_regs0 = 6'd0; +reg [5:0] builder_multiregimpl5_regs1 = 6'd0; +reg [5:0] builder_multiregimpl6_regs0 = 6'd0; +reg [5:0] builder_multiregimpl6_regs1 = 6'd0; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign main_wb_bus_adr = wishbone_adr; +assign main_wb_bus_dat_w = wishbone_dat_w; +assign wishbone_dat_r = main_wb_bus_dat_r; +assign main_wb_bus_sel = wishbone_sel; +assign main_wb_bus_cyc = wishbone_cyc; +assign main_wb_bus_stb = wishbone_stb; +assign wishbone_ack = main_wb_bus_ack; +assign main_wb_bus_we = wishbone_we; +assign main_wb_bus_cti = wishbone_cti; +assign main_wb_bus_bte = wishbone_bte; +assign wishbone_err = main_wb_bus_err; +assign interrupt = main_sram167_irq; +assign main_maccore_maccore_bus_error = builder_error; +assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors; +assign sys_clk = sys_clock; +assign por_clk = sys_clock; +assign sys_rst = main_maccore_int_rst; +assign eth_rx_clk = rgmii_eth_clocks_rx; +assign eth_tx_clk = eth_rx_clk; +assign main_maccore_ethphy_reset = main_maccore_ethphy_reset_storage; +assign rgmii_eth_rst_n = (~main_maccore_ethphy_reset); +assign main_maccore_ethphy_sink_ready = 1'd1; +assign main_maccore_ethphy_last = ((~main_maccore_ethphy_rx_ctl_reg[0]) & main_maccore_ethphy_rx_ctl_reg_d[0]); +assign main_maccore_ethphy_source_last = main_maccore_ethphy_last; +assign rgmii_eth_mdc = main_maccore_ethphy__w_storage[0]; +assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1]; +assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2]; +assign main_sink_valid = main_source_source_valid; +assign main_source_source_ready = main_sink_ready; +assign main_sink_first = main_source_source_first; +assign main_sink_last = main_source_source_last; +assign main_sink_payload_data = main_source_source_payload_data; +assign main_sink_payload_last_be = main_source_source_payload_last_be; +assign main_sink_payload_error = main_source_source_payload_error; +assign main_sink_sink_valid = main_source_valid; +assign main_source_ready = main_sink_sink_ready; +assign main_sink_sink_first = main_source_first; +assign main_sink_sink_last = main_source_last; +assign main_sink_sink_payload_data = main_source_payload_data; +assign main_sink_sink_payload_last_be = main_source_payload_last_be; +assign main_sink_sink_payload_error = main_source_payload_error; +assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; +assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; +assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; +assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; +assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; +assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; +assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; +assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; +assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; +assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; +assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; +assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; +assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; +assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; +assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; +assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; +assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; +assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; +assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; +assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; +assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; +assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; +assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; +assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; +assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; +assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; +assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; +assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; +assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; +assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; +assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); +assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); +assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); +assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); +assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; +assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; +assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; +assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; +always @(*) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter0_ce) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); +always @(*) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter1_ce) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; +assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; +assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; +assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; +always @(*) begin + main_tx_converter_converter_sink_payload_data <= 40'd0; + main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; + main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; + main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; + main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; + main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; + main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; + main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; + main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; + main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; + main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; + main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; + main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; +end +assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; +assign main_tx_converter_source_first = main_tx_converter_source_source_first; +assign main_tx_converter_source_last = main_tx_converter_source_source_last; +assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; +assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; +assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; +assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; +assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; +assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; +assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; +assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); +assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); +assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; +assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); +assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); +assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); +always @(*) begin + main_tx_converter_converter_source_payload_data <= 10'd0; + case (main_tx_converter_converter_mux) + 1'd0: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; + end + 1'd1: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; + end + 2'd2: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; + end + default: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; + end + endcase +end +assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; +always @(*) begin + main_tx_last_be_source_valid <= 1'd0; + main_tx_last_be_source_first <= 1'd0; + main_tx_last_be_source_last <= 1'd0; + main_tx_last_be_source_payload_data <= 8'd0; + builder_maccore_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + main_tx_last_be_source_payload_last_be <= 1'd0; + main_tx_last_be_source_payload_error <= 1'd0; + main_tx_last_be_sink_ready <= 1'd0; + builder_maccore_txdatapath_liteethmactxlastbe_next_state <= builder_maccore_txdatapath_liteethmactxlastbe_state; + case (builder_maccore_txdatapath_liteethmactxlastbe_state) + 1'd1: begin + main_tx_last_be_sink_ready <= 1'd1; + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin + builder_maccore_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + end + end + default: begin + main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; + main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; + main_tx_last_be_source_first <= main_tx_last_be_sink_first; + main_tx_last_be_source_last <= main_tx_last_be_sink_last; + main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; + main_tx_last_be_source_payload_last_be <= main_tx_last_be_sink_payload_last_be; + main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; + main_tx_last_be_source_last <= (main_tx_last_be_sink_payload_last_be != 1'd0); + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin + if ((main_tx_last_be_source_last & (~main_tx_last_be_sink_last))) begin + builder_maccore_txdatapath_liteethmactxlastbe_next_state <= 1'd1; + end + end + end + endcase +end +assign main_tx_padding_counter_done = (main_tx_padding_counter >= 6'd59); +always @(*) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; + main_tx_padding_source_valid <= 1'd0; + main_tx_padding_source_first <= 1'd0; + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_data <= 8'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + main_tx_padding_source_payload_error <= 1'd0; + main_tx_padding_sink_ready <= 1'd0; + builder_maccore_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; + builder_maccore_txdatapath_liteethmacpaddinginserter_next_state <= builder_maccore_txdatapath_liteethmacpaddinginserter_state; + case (builder_maccore_txdatapath_liteethmacpaddinginserter_state) + 1'd1: begin + main_tx_padding_source_valid <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_source_payload_last_be <= 1'd1; + main_tx_padding_source_last <= 1'd1; + end + main_tx_padding_source_payload_data <= 1'd0; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + builder_maccore_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + end + end + end + default: begin + main_tx_padding_source_valid <= main_tx_padding_sink_valid; + main_tx_padding_sink_ready <= main_tx_padding_source_ready; + main_tx_padding_source_first <= main_tx_padding_sink_first; + main_tx_padding_source_last <= main_tx_padding_sink_last; + main_tx_padding_source_payload_data <= main_tx_padding_sink_payload_data; + main_tx_padding_source_payload_last_be <= main_tx_padding_sink_payload_last_be; + main_tx_padding_source_payload_error <= main_tx_padding_sink_payload_error; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_sink_last) begin + if ((~main_tx_padding_counter_done)) begin + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + builder_maccore_txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; + end else begin + if (((main_tx_padding_counter == 6'd59) & (main_tx_padding_sink_payload_last_be < 1'd1))) begin + main_tx_padding_source_payload_last_be <= 1'd1; + end else begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + end + end + end + end + end + endcase +end +assign main_liteethmaccrc32inserter_cnt_done = (main_liteethmaccrc32inserter_cnt == 1'd0); +assign main_liteethmaccrc32inserter_sink_valid = main_bufferizeendpoints_source_valid; +assign main_bufferizeendpoints_source_ready = main_liteethmaccrc32inserter_sink_ready; +assign main_liteethmaccrc32inserter_sink_first = main_bufferizeendpoints_source_first; +assign main_liteethmaccrc32inserter_sink_last = main_bufferizeendpoints_source_last; +assign main_liteethmaccrc32inserter_sink_payload_data = main_bufferizeendpoints_source_payload_data; +assign main_liteethmaccrc32inserter_sink_payload_last_be = main_bufferizeendpoints_source_payload_last_be; +assign main_liteethmaccrc32inserter_sink_payload_error = main_bufferizeendpoints_source_payload_error; +always @(*) begin + main_liteethmaccrc32inserter_last_be1 <= 1'd0; + if ((main_liteethmaccrc32inserter_last_be0 != 1'd0)) begin + main_liteethmaccrc32inserter_last_be1 <= main_liteethmaccrc32inserter_last_be0; + end else begin + main_liteethmaccrc32inserter_last_be1 <= 1'd1; + end +end +assign main_liteethmaccrc32inserter_data1 = main_liteethmaccrc32inserter_data0[7:0]; +assign main_liteethmaccrc32inserter_last = main_liteethmaccrc32inserter_reg; +always @(*) begin + main_liteethmaccrc32inserter_value <= 32'd0; + main_liteethmaccrc32inserter_error <= 1'd0; + if (main_liteethmaccrc32inserter_last_be1) begin + main_liteethmaccrc32inserter_value <= {builder_t_slice_proxy31[0], builder_t_slice_proxy30[1], builder_t_slice_proxy29[2], builder_t_slice_proxy28[3], builder_t_slice_proxy27[4], builder_t_slice_proxy26[5], builder_t_slice_proxy25[6], builder_t_slice_proxy24[7], builder_t_slice_proxy23[8], builder_t_slice_proxy22[9], builder_t_slice_proxy21[10], builder_t_slice_proxy20[11], builder_t_slice_proxy19[12], builder_t_slice_proxy18[13], builder_t_slice_proxy17[14], builder_t_slice_proxy16[15], builder_t_slice_proxy15[16], builder_t_slice_proxy14[17], builder_t_slice_proxy13[18], builder_t_slice_proxy12[19], builder_t_slice_proxy11[20], builder_t_slice_proxy10[21], builder_t_slice_proxy9[22], builder_t_slice_proxy8[23], builder_t_slice_proxy7[24], builder_t_slice_proxy6[25], builder_t_slice_proxy5[26], builder_t_slice_proxy4[27], builder_t_slice_proxy3[28], builder_t_slice_proxy2[29], builder_t_slice_proxy1[30], builder_t_slice_proxy0[31]}; + main_liteethmaccrc32inserter_error <= (main_liteethmaccrc32inserter_next != 32'd3338984827); + end +end +always @(*) begin + main_liteethmaccrc32inserter_next <= 32'd0; + main_liteethmaccrc32inserter_next[0] <= (((main_liteethmaccrc32inserter_last[24] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); + main_liteethmaccrc32inserter_next[1] <= (((((((main_liteethmaccrc32inserter_last[25] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); + main_liteethmaccrc32inserter_next[2] <= (((((((((main_liteethmaccrc32inserter_last[26] ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); + main_liteethmaccrc32inserter_next[3] <= (((((((main_liteethmaccrc32inserter_last[27] ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); + main_liteethmaccrc32inserter_next[4] <= (((((((((main_liteethmaccrc32inserter_last[28] ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); + main_liteethmaccrc32inserter_next[5] <= (((((((((((((main_liteethmaccrc32inserter_last[29] ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); + main_liteethmaccrc32inserter_next[6] <= (((((((((((main_liteethmaccrc32inserter_last[30] ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); + main_liteethmaccrc32inserter_next[7] <= (((((((((main_liteethmaccrc32inserter_last[31] ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); + main_liteethmaccrc32inserter_next[8] <= ((((((((main_liteethmaccrc32inserter_last[0] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); + main_liteethmaccrc32inserter_next[9] <= ((((((((main_liteethmaccrc32inserter_last[1] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]); + main_liteethmaccrc32inserter_next[10] <= ((((((((main_liteethmaccrc32inserter_last[2] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); + main_liteethmaccrc32inserter_next[11] <= ((((((((main_liteethmaccrc32inserter_last[3] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); + main_liteethmaccrc32inserter_next[12] <= ((((((((((((main_liteethmaccrc32inserter_last[4] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); + main_liteethmaccrc32inserter_next[13] <= ((((((((((((main_liteethmaccrc32inserter_last[5] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); + main_liteethmaccrc32inserter_next[14] <= ((((((((((main_liteethmaccrc32inserter_last[6] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); + main_liteethmaccrc32inserter_next[15] <= ((((((((main_liteethmaccrc32inserter_last[7] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); + main_liteethmaccrc32inserter_next[16] <= ((((((main_liteethmaccrc32inserter_last[8] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); + main_liteethmaccrc32inserter_next[17] <= ((((((main_liteethmaccrc32inserter_last[9] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]); + main_liteethmaccrc32inserter_next[18] <= ((((((main_liteethmaccrc32inserter_last[10] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); + main_liteethmaccrc32inserter_next[19] <= ((((main_liteethmaccrc32inserter_last[11] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); + main_liteethmaccrc32inserter_next[20] <= ((main_liteethmaccrc32inserter_last[12] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]); + main_liteethmaccrc32inserter_next[21] <= ((main_liteethmaccrc32inserter_last[13] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]); + main_liteethmaccrc32inserter_next[22] <= ((main_liteethmaccrc32inserter_last[14] ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); + main_liteethmaccrc32inserter_next[23] <= ((((((main_liteethmaccrc32inserter_last[15] ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); + main_liteethmaccrc32inserter_next[24] <= ((((((main_liteethmaccrc32inserter_last[16] ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); + main_liteethmaccrc32inserter_next[25] <= ((((main_liteethmaccrc32inserter_last[17] ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); + main_liteethmaccrc32inserter_next[26] <= ((((((((main_liteethmaccrc32inserter_last[18] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); + main_liteethmaccrc32inserter_next[27] <= ((((((((main_liteethmaccrc32inserter_last[19] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); + main_liteethmaccrc32inserter_next[28] <= ((((((main_liteethmaccrc32inserter_last[20] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); + main_liteethmaccrc32inserter_next[29] <= ((((((main_liteethmaccrc32inserter_last[21] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); + main_liteethmaccrc32inserter_next[30] <= ((((main_liteethmaccrc32inserter_last[22] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]); + main_liteethmaccrc32inserter_next[31] <= ((main_liteethmaccrc32inserter_last[23] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]); +end +always @(*) begin + main_liteethmaccrc32inserter_source_last <= 1'd0; + main_liteethmaccrc32inserter_source_payload_data <= 8'd0; + main_liteethmaccrc32inserter_source_payload_last_be <= 1'd0; + main_liteethmaccrc32inserter_source_payload_error <= 1'd0; + main_liteethmaccrc32inserter_data0 <= 8'd0; + main_liteethmaccrc32inserter_last_be0 <= 1'd0; + builder_maccore_txdatapath_bufferizeendpoints_next_state <= 2'd0; + main_liteethmaccrc32inserter_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; + main_liteethmaccrc32inserter_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; + main_liteethmaccrc32inserter_last_be2_clockdomainsrenamer1_next_value1 <= 1'd0; + main_liteethmaccrc32inserter_last_be2_clockdomainsrenamer1_next_value_ce1 <= 1'd0; + main_liteethmaccrc32inserter_sink_ready <= 1'd0; + main_liteethmaccrc32inserter_is_ongoing0 <= 1'd0; + main_liteethmaccrc32inserter_is_ongoing1 <= 1'd0; + main_liteethmaccrc32inserter_source_valid <= 1'd0; + main_liteethmaccrc32inserter_ce <= 1'd0; + main_liteethmaccrc32inserter_reset <= 1'd0; + main_liteethmaccrc32inserter_source_first <= 1'd0; + builder_maccore_txdatapath_bufferizeendpoints_next_state <= builder_maccore_txdatapath_bufferizeendpoints_state; + case (builder_maccore_txdatapath_bufferizeendpoints_state) + 1'd1: begin + main_liteethmaccrc32inserter_ce <= (main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_source_ready); + main_liteethmaccrc32inserter_data0 <= main_liteethmaccrc32inserter_sink_payload_data; + main_liteethmaccrc32inserter_last_be0 <= main_liteethmaccrc32inserter_sink_payload_last_be; + main_liteethmaccrc32inserter_source_valid <= main_liteethmaccrc32inserter_sink_valid; + main_liteethmaccrc32inserter_sink_ready <= main_liteethmaccrc32inserter_source_ready; + main_liteethmaccrc32inserter_source_first <= main_liteethmaccrc32inserter_sink_first; + main_liteethmaccrc32inserter_source_last <= main_liteethmaccrc32inserter_sink_last; + main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_sink_payload_data; + main_liteethmaccrc32inserter_source_payload_last_be <= main_liteethmaccrc32inserter_sink_payload_last_be; + main_liteethmaccrc32inserter_source_payload_error <= main_liteethmaccrc32inserter_sink_payload_error; + main_liteethmaccrc32inserter_source_last <= 1'd0; + main_liteethmaccrc32inserter_source_payload_last_be <= 1'd0; + if (main_liteethmaccrc32inserter_sink_last) begin + if (main_liteethmaccrc32inserter_sink_payload_last_be) begin + main_liteethmaccrc32inserter_source_payload_data <= builder_cases_slice_proxy[7:0]; + end + if ((1'd0 & (main_liteethmaccrc32inserter_sink_payload_last_be <= 4'd15))) begin + main_liteethmaccrc32inserter_source_last <= 1'd1; + main_liteethmaccrc32inserter_source_payload_last_be <= (main_liteethmaccrc32inserter_sink_payload_last_be <<< -3'd3); + end + end else begin + main_liteethmaccrc32inserter_ce <= (main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_source_ready); + end + if (((main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_sink_last) & main_liteethmaccrc32inserter_source_ready)) begin + if ((1'd0 & (main_liteethmaccrc32inserter_sink_payload_last_be <= 4'd15))) begin + builder_maccore_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end else begin + main_liteethmaccrc32inserter_crc_packet_clockdomainsrenamer1_next_value0 <= main_liteethmaccrc32inserter_value; + main_liteethmaccrc32inserter_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; + if (1'd0) begin + main_liteethmaccrc32inserter_last_be2_clockdomainsrenamer1_next_value1 <= (main_liteethmaccrc32inserter_sink_payload_last_be >>> 3'd4); + main_liteethmaccrc32inserter_last_be2_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end else begin + main_liteethmaccrc32inserter_last_be2_clockdomainsrenamer1_next_value1 <= main_liteethmaccrc32inserter_sink_payload_last_be; + main_liteethmaccrc32inserter_last_be2_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end + builder_maccore_txdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_liteethmaccrc32inserter_source_valid <= 1'd1; + case (main_liteethmaccrc32inserter_cnt) + 1'd0: begin + main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_crc_packet[31:24]; + end + 1'd1: begin + main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_crc_packet[23:16]; + end + 2'd2: begin + main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_crc_packet[15:8]; + end + default: begin + main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_crc_packet[7:0]; + end + endcase + if (main_liteethmaccrc32inserter_cnt_done) begin + main_liteethmaccrc32inserter_source_last <= 1'd1; + if (main_liteethmaccrc32inserter_source_ready) begin + builder_maccore_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + main_liteethmaccrc32inserter_is_ongoing1 <= 1'd1; + end + default: begin + main_liteethmaccrc32inserter_reset <= 1'd1; + main_liteethmaccrc32inserter_sink_ready <= 1'd1; + if (main_liteethmaccrc32inserter_sink_valid) begin + main_liteethmaccrc32inserter_sink_ready <= 1'd0; + builder_maccore_txdatapath_bufferizeendpoints_next_state <= 1'd1; + end + main_liteethmaccrc32inserter_is_ongoing0 <= 1'd1; + end + endcase +end +assign main_bufferizeendpoints_sink_ready = ((~main_bufferizeendpoints_source_valid) | main_bufferizeendpoints_source_ready); +assign main_tx_preamble_source_payload_last_be = main_tx_preamble_sink_payload_last_be; +always @(*) begin + builder_maccore_txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; + main_tx_preamble_source_valid <= 1'd0; + main_tx_preamble_source_first <= 1'd0; + main_tx_preamble_source_last <= 1'd0; + main_tx_preamble_source_payload_data <= 8'd0; + main_tx_preamble_source_payload_error <= 1'd0; + main_tx_preamble_sink_ready <= 1'd0; + main_tx_preamble_source_payload_data <= main_tx_preamble_sink_payload_data; + builder_maccore_txdatapath_liteethmacpreambleinserter_next_state <= builder_maccore_txdatapath_liteethmacpreambleinserter_state; + case (builder_maccore_txdatapath_liteethmacpreambleinserter_state) + 1'd1: begin + main_tx_preamble_source_valid <= 1'd1; + case (main_tx_preamble_count) + 1'd0: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[7:0]; + end + 1'd1: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[15:8]; + end + 2'd2: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[23:16]; + end + 2'd3: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[31:24]; + end + 3'd4: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[39:32]; + end + 3'd5: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[47:40]; + end + 3'd6: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[55:48]; + end + default: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[63:56]; + end + endcase + if (main_tx_preamble_source_ready) begin + if ((main_tx_preamble_count == 3'd7)) begin + builder_maccore_txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; + end else begin + main_tx_preamble_count_clockdomainsrenamer2_next_value <= (main_tx_preamble_count + 1'd1); + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + end + end + end + 2'd2: begin + main_tx_preamble_source_valid <= main_tx_preamble_sink_valid; + main_tx_preamble_sink_ready <= main_tx_preamble_source_ready; + main_tx_preamble_source_first <= main_tx_preamble_sink_first; + main_tx_preamble_source_last <= main_tx_preamble_sink_last; + main_tx_preamble_source_payload_error <= main_tx_preamble_sink_payload_error; + if (((main_tx_preamble_sink_valid & main_tx_preamble_sink_last) & main_tx_preamble_source_ready)) begin + builder_maccore_txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; + end + end + default: begin + main_tx_preamble_sink_ready <= 1'd1; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + if (main_tx_preamble_sink_valid) begin + main_tx_preamble_sink_ready <= 1'd0; + builder_maccore_txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; + main_tx_gap_source_valid <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; + main_tx_gap_source_first <= 1'd0; + main_tx_gap_source_last <= 1'd0; + main_tx_gap_source_payload_data <= 8'd0; + main_tx_gap_source_payload_last_be <= 1'd0; + main_tx_gap_source_payload_error <= 1'd0; + main_tx_gap_sink_ready <= 1'd0; + builder_maccore_txdatapath_liteethmacgap_next_state <= 1'd0; + builder_maccore_txdatapath_liteethmacgap_next_state <= builder_maccore_txdatapath_liteethmacgap_state; + case (builder_maccore_txdatapath_liteethmacgap_state) + 1'd1: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= (main_tx_gap_counter + 1'd1); + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + if ((main_tx_gap_counter == 4'd11)) begin + builder_maccore_txdatapath_liteethmacgap_next_state <= 1'd0; + end + end + default: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + main_tx_gap_source_valid <= main_tx_gap_sink_valid; + main_tx_gap_sink_ready <= main_tx_gap_source_ready; + main_tx_gap_source_first <= main_tx_gap_sink_first; + main_tx_gap_source_last <= main_tx_gap_sink_last; + main_tx_gap_source_payload_data <= main_tx_gap_sink_payload_data; + main_tx_gap_source_payload_last_be <= main_tx_gap_sink_payload_last_be; + main_tx_gap_source_payload_error <= main_tx_gap_sink_payload_error; + if (((main_tx_gap_sink_valid & main_tx_gap_sink_last) & main_tx_gap_sink_ready)) begin + builder_maccore_txdatapath_liteethmacgap_next_state <= 1'd1; + end + end + endcase +end +assign main_tx_cdc_sink_sink_valid = main_sink_valid; +assign main_sink_ready = main_tx_cdc_sink_sink_ready; +assign main_tx_cdc_sink_sink_first = main_sink_first; +assign main_tx_cdc_sink_sink_last = main_sink_last; +assign main_tx_cdc_sink_sink_payload_data = main_sink_payload_data; +assign main_tx_cdc_sink_sink_payload_last_be = main_sink_payload_last_be; +assign main_tx_cdc_sink_sink_payload_error = main_sink_payload_error; +assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; +assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; +assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; +assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; +assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; +assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; +assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; +assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; +assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; +assign main_tx_last_be_sink_first = main_tx_converter_source_first; +assign main_tx_last_be_sink_last = main_tx_converter_source_last; +assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; +assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; +assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; +assign main_tx_padding_sink_valid = main_tx_last_be_source_valid; +assign main_tx_last_be_source_ready = main_tx_padding_sink_ready; +assign main_tx_padding_sink_first = main_tx_last_be_source_first; +assign main_tx_padding_sink_last = main_tx_last_be_source_last; +assign main_tx_padding_sink_payload_data = main_tx_last_be_source_payload_data; +assign main_tx_padding_sink_payload_last_be = main_tx_last_be_source_payload_last_be; +assign main_tx_padding_sink_payload_error = main_tx_last_be_source_payload_error; +assign main_bufferizeendpoints_sink_valid = main_tx_padding_source_valid; +assign main_tx_padding_source_ready = main_bufferizeendpoints_sink_ready; +assign main_bufferizeendpoints_sink_first = main_tx_padding_source_first; +assign main_bufferizeendpoints_sink_last = main_tx_padding_source_last; +assign main_bufferizeendpoints_sink_payload_data = main_tx_padding_source_payload_data; +assign main_bufferizeendpoints_sink_payload_last_be = main_tx_padding_source_payload_last_be; +assign main_bufferizeendpoints_sink_payload_error = main_tx_padding_source_payload_error; +assign main_tx_preamble_sink_valid = main_liteethmaccrc32inserter_source_valid; +assign main_liteethmaccrc32inserter_source_ready = main_tx_preamble_sink_ready; +assign main_tx_preamble_sink_first = main_liteethmaccrc32inserter_source_first; +assign main_tx_preamble_sink_last = main_liteethmaccrc32inserter_source_last; +assign main_tx_preamble_sink_payload_data = main_liteethmaccrc32inserter_source_payload_data; +assign main_tx_preamble_sink_payload_last_be = main_liteethmaccrc32inserter_source_payload_last_be; +assign main_tx_preamble_sink_payload_error = main_liteethmaccrc32inserter_source_payload_error; +assign main_tx_gap_sink_valid = main_tx_preamble_source_valid; +assign main_tx_preamble_source_ready = main_tx_gap_sink_ready; +assign main_tx_gap_sink_first = main_tx_preamble_source_first; +assign main_tx_gap_sink_last = main_tx_preamble_source_last; +assign main_tx_gap_sink_payload_data = main_tx_preamble_source_payload_data; +assign main_tx_gap_sink_payload_last_be = main_tx_preamble_source_payload_last_be; +assign main_tx_gap_sink_payload_error = main_tx_preamble_source_payload_error; +assign main_maccore_ethphy_sink_valid = main_tx_gap_source_valid; +assign main_tx_gap_source_ready = main_maccore_ethphy_sink_ready; +assign main_maccore_ethphy_sink_first = main_tx_gap_source_first; +assign main_maccore_ethphy_sink_last = main_tx_gap_source_last; +assign main_maccore_ethphy_sink_payload_data = main_tx_gap_source_payload_data; +assign main_maccore_ethphy_sink_payload_last_be = main_tx_gap_source_payload_last_be; +assign main_maccore_ethphy_sink_payload_error = main_tx_gap_source_payload_error; +assign main_pulsesynchronizer0_i = main_rx_preamble_error; +assign main_pulsesynchronizer1_i = main_rx_crc_error; +assign main_rx_preamble_source_payload_data = main_rx_preamble_sink_payload_data; +assign main_rx_preamble_source_payload_last_be = main_rx_preamble_sink_payload_last_be; +always @(*) begin + main_rx_preamble_error <= 1'd0; + main_rx_preamble_source_first <= 1'd0; + main_rx_preamble_source_valid <= 1'd0; + builder_maccore_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + main_rx_preamble_sink_ready <= 1'd0; + main_rx_preamble_source_last <= 1'd0; + main_rx_preamble_source_payload_error <= 1'd0; + builder_maccore_rxdatapath_liteethmacpreamblechecker_next_state <= builder_maccore_rxdatapath_liteethmacpreamblechecker_state; + case (builder_maccore_rxdatapath_liteethmacpreamblechecker_state) + 1'd1: begin + main_rx_preamble_source_valid <= main_rx_preamble_sink_valid; + main_rx_preamble_sink_ready <= main_rx_preamble_source_ready; + main_rx_preamble_source_first <= main_rx_preamble_sink_first; + main_rx_preamble_source_last <= main_rx_preamble_sink_last; + main_rx_preamble_source_payload_error <= main_rx_preamble_sink_payload_error; + if (((main_rx_preamble_source_valid & main_rx_preamble_source_last) & main_rx_preamble_source_ready)) begin + builder_maccore_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + end + end + default: begin + main_rx_preamble_sink_ready <= 1'd1; + if (((main_rx_preamble_sink_valid & (~main_rx_preamble_sink_last)) & (main_rx_preamble_sink_payload_data == main_rx_preamble_preamble[63:56]))) begin + builder_maccore_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; + end + if ((main_rx_preamble_sink_valid & main_rx_preamble_sink_last)) begin + main_rx_preamble_error <= 1'd1; + end + end + endcase +end +assign main_pulsesynchronizer0_o = (main_pulsesynchronizer0_toggle_o ^ main_pulsesynchronizer0_toggle_o_r); +assign main_rx_crc_fifo_full = (main_rx_crc_syncfifo_level == 3'd4); +assign main_rx_crc_fifo_in = (main_rx_crc_sink_sink_valid & ((~main_rx_crc_fifo_full) | main_rx_crc_fifo_out)); +assign main_rx_crc_fifo_out = (main_rx_crc_source_source_valid & main_rx_crc_source_source_ready); +assign main_rx_crc_syncfifo_sink_first = main_rx_crc_sink_sink_first; +assign main_rx_crc_syncfifo_sink_last = main_rx_crc_sink_sink_last; +assign main_rx_crc_syncfifo_sink_payload_data = main_rx_crc_sink_sink_payload_data; +assign main_rx_crc_syncfifo_sink_payload_last_be = main_rx_crc_sink_sink_payload_last_be; +assign main_rx_crc_syncfifo_sink_payload_error = main_rx_crc_sink_sink_payload_error; +always @(*) begin + main_rx_crc_syncfifo_sink_valid <= 1'd0; + main_rx_crc_syncfifo_sink_valid <= main_rx_crc_sink_sink_valid; + main_rx_crc_syncfifo_sink_valid <= main_rx_crc_fifo_in; +end +always @(*) begin + main_rx_crc_sink_sink_ready <= 1'd0; + main_rx_crc_sink_sink_ready <= main_rx_crc_syncfifo_sink_ready; + main_rx_crc_sink_sink_ready <= main_rx_crc_fifo_in; +end +assign main_rx_crc_crc_data0 = main_rx_crc_sink_sink_payload_data; +assign main_rx_crc_crc_last_be0 = main_rx_crc_sink_sink_payload_last_be; +assign main_rx_crc_sink_sink_valid = main_rx_crc_source_valid; +assign main_rx_crc_source_ready = main_rx_crc_sink_sink_ready; +assign main_rx_crc_sink_sink_first = main_rx_crc_source_first; +assign main_rx_crc_sink_sink_last = main_rx_crc_source_last; +assign main_rx_crc_sink_sink_payload_data = main_rx_crc_source_payload_data; +assign main_rx_crc_sink_sink_payload_last_be = main_rx_crc_source_payload_last_be; +assign main_rx_crc_sink_sink_payload_error = main_rx_crc_source_payload_error; +always @(*) begin + main_rx_crc_crc_last_be1 <= 1'd0; + if ((main_rx_crc_crc_last_be0 != 1'd0)) begin + main_rx_crc_crc_last_be1 <= main_rx_crc_crc_last_be0; + end else begin + main_rx_crc_crc_last_be1 <= 1'd1; + end +end +assign main_rx_crc_crc_data1 = main_rx_crc_crc_data0[7:0]; +assign main_rx_crc_crc_last = main_rx_crc_crc_reg; +always @(*) begin + main_rx_crc_crc_value <= 32'd0; + main_rx_crc_crc_error0 <= 1'd0; + if (main_rx_crc_crc_last_be1) begin + main_rx_crc_crc_value <= {builder_t_slice_proxy63[0], builder_t_slice_proxy62[1], builder_t_slice_proxy61[2], builder_t_slice_proxy60[3], builder_t_slice_proxy59[4], builder_t_slice_proxy58[5], builder_t_slice_proxy57[6], builder_t_slice_proxy56[7], builder_t_slice_proxy55[8], builder_t_slice_proxy54[9], builder_t_slice_proxy53[10], builder_t_slice_proxy52[11], builder_t_slice_proxy51[12], builder_t_slice_proxy50[13], builder_t_slice_proxy49[14], builder_t_slice_proxy48[15], builder_t_slice_proxy47[16], builder_t_slice_proxy46[17], builder_t_slice_proxy45[18], builder_t_slice_proxy44[19], builder_t_slice_proxy43[20], builder_t_slice_proxy42[21], builder_t_slice_proxy41[22], builder_t_slice_proxy40[23], builder_t_slice_proxy39[24], builder_t_slice_proxy38[25], builder_t_slice_proxy37[26], builder_t_slice_proxy36[27], builder_t_slice_proxy35[28], builder_t_slice_proxy34[29], builder_t_slice_proxy33[30], builder_t_slice_proxy32[31]}; + main_rx_crc_crc_error0 <= (main_rx_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + main_rx_crc_crc_next <= 32'd0; + main_rx_crc_crc_next[0] <= (((main_rx_crc_crc_last[24] ^ main_rx_crc_crc_last[30]) ^ main_rx_crc_crc_data1[1]) ^ main_rx_crc_crc_data1[7]); + main_rx_crc_crc_next[1] <= (((((((main_rx_crc_crc_last[25] ^ main_rx_crc_crc_last[31]) ^ main_rx_crc_crc_data1[0]) ^ main_rx_crc_crc_data1[6]) ^ main_rx_crc_crc_last[24]) ^ main_rx_crc_crc_last[30]) ^ main_rx_crc_crc_data1[1]) ^ main_rx_crc_crc_data1[7]); + main_rx_crc_crc_next[2] <= (((((((((main_rx_crc_crc_last[26] ^ main_rx_crc_crc_data1[5]) ^ main_rx_crc_crc_last[25]) ^ main_rx_crc_crc_last[31]) ^ main_rx_crc_crc_data1[0]) ^ main_rx_crc_crc_data1[6]) ^ main_rx_crc_crc_last[24]) ^ main_rx_crc_crc_last[30]) ^ main_rx_crc_crc_data1[1]) ^ main_rx_crc_crc_data1[7]); + main_rx_crc_crc_next[3] <= (((((((main_rx_crc_crc_last[27] ^ main_rx_crc_crc_data1[4]) ^ main_rx_crc_crc_last[26]) ^ main_rx_crc_crc_data1[5]) ^ main_rx_crc_crc_last[25]) ^ main_rx_crc_crc_last[31]) ^ main_rx_crc_crc_data1[0]) ^ main_rx_crc_crc_data1[6]); + main_rx_crc_crc_next[4] <= (((((((((main_rx_crc_crc_last[28] ^ main_rx_crc_crc_data1[3]) ^ main_rx_crc_crc_last[27]) ^ main_rx_crc_crc_data1[4]) ^ main_rx_crc_crc_last[26]) ^ main_rx_crc_crc_data1[5]) ^ main_rx_crc_crc_last[24]) ^ main_rx_crc_crc_last[30]) ^ main_rx_crc_crc_data1[1]) ^ main_rx_crc_crc_data1[7]); + main_rx_crc_crc_next[5] <= (((((((((((((main_rx_crc_crc_last[29] ^ main_rx_crc_crc_data1[2]) ^ main_rx_crc_crc_last[28]) ^ main_rx_crc_crc_data1[3]) ^ main_rx_crc_crc_last[27]) ^ main_rx_crc_crc_data1[4]) ^ main_rx_crc_crc_last[25]) ^ main_rx_crc_crc_last[31]) ^ main_rx_crc_crc_data1[0]) ^ main_rx_crc_crc_data1[6]) ^ main_rx_crc_crc_last[24]) ^ main_rx_crc_crc_last[30]) ^ main_rx_crc_crc_data1[1]) ^ main_rx_crc_crc_data1[7]); + main_rx_crc_crc_next[6] <= (((((((((((main_rx_crc_crc_last[30] ^ main_rx_crc_crc_data1[1]) ^ main_rx_crc_crc_last[29]) ^ main_rx_crc_crc_data1[2]) ^ main_rx_crc_crc_last[28]) ^ main_rx_crc_crc_data1[3]) ^ main_rx_crc_crc_last[26]) ^ main_rx_crc_crc_data1[5]) ^ main_rx_crc_crc_last[25]) ^ main_rx_crc_crc_last[31]) ^ main_rx_crc_crc_data1[0]) ^ main_rx_crc_crc_data1[6]); + main_rx_crc_crc_next[7] <= (((((((((main_rx_crc_crc_last[31] ^ main_rx_crc_crc_data1[0]) ^ main_rx_crc_crc_last[29]) ^ main_rx_crc_crc_data1[2]) ^ main_rx_crc_crc_last[27]) ^ main_rx_crc_crc_data1[4]) ^ main_rx_crc_crc_last[26]) ^ main_rx_crc_crc_data1[5]) ^ main_rx_crc_crc_last[24]) ^ main_rx_crc_crc_data1[7]); + main_rx_crc_crc_next[8] <= ((((((((main_rx_crc_crc_last[0] ^ main_rx_crc_crc_last[28]) ^ main_rx_crc_crc_data1[3]) ^ main_rx_crc_crc_last[27]) ^ main_rx_crc_crc_data1[4]) ^ main_rx_crc_crc_last[25]) ^ main_rx_crc_crc_data1[6]) ^ main_rx_crc_crc_last[24]) ^ main_rx_crc_crc_data1[7]); + main_rx_crc_crc_next[9] <= ((((((((main_rx_crc_crc_last[1] ^ main_rx_crc_crc_last[29]) ^ main_rx_crc_crc_data1[2]) ^ main_rx_crc_crc_last[28]) ^ main_rx_crc_crc_data1[3]) ^ main_rx_crc_crc_last[26]) ^ main_rx_crc_crc_data1[5]) ^ main_rx_crc_crc_last[25]) ^ main_rx_crc_crc_data1[6]); + main_rx_crc_crc_next[10] <= ((((((((main_rx_crc_crc_last[2] ^ main_rx_crc_crc_last[29]) ^ main_rx_crc_crc_data1[2]) ^ main_rx_crc_crc_last[27]) ^ main_rx_crc_crc_data1[4]) ^ main_rx_crc_crc_last[26]) ^ main_rx_crc_crc_data1[5]) ^ main_rx_crc_crc_last[24]) ^ main_rx_crc_crc_data1[7]); + main_rx_crc_crc_next[11] <= ((((((((main_rx_crc_crc_last[3] ^ main_rx_crc_crc_last[28]) ^ main_rx_crc_crc_data1[3]) ^ main_rx_crc_crc_last[27]) ^ main_rx_crc_crc_data1[4]) ^ main_rx_crc_crc_last[25]) ^ main_rx_crc_crc_data1[6]) ^ main_rx_crc_crc_last[24]) ^ main_rx_crc_crc_data1[7]); + main_rx_crc_crc_next[12] <= ((((((((((((main_rx_crc_crc_last[4] ^ main_rx_crc_crc_last[29]) ^ main_rx_crc_crc_data1[2]) ^ main_rx_crc_crc_last[28]) ^ main_rx_crc_crc_data1[3]) ^ main_rx_crc_crc_last[26]) ^ main_rx_crc_crc_data1[5]) ^ main_rx_crc_crc_last[25]) ^ main_rx_crc_crc_data1[6]) ^ main_rx_crc_crc_last[24]) ^ main_rx_crc_crc_last[30]) ^ main_rx_crc_crc_data1[1]) ^ main_rx_crc_crc_data1[7]); + main_rx_crc_crc_next[13] <= ((((((((((((main_rx_crc_crc_last[5] ^ main_rx_crc_crc_last[30]) ^ main_rx_crc_crc_data1[1]) ^ main_rx_crc_crc_last[29]) ^ main_rx_crc_crc_data1[2]) ^ main_rx_crc_crc_last[27]) ^ main_rx_crc_crc_data1[4]) ^ main_rx_crc_crc_last[26]) ^ main_rx_crc_crc_data1[5]) ^ main_rx_crc_crc_last[25]) ^ main_rx_crc_crc_last[31]) ^ main_rx_crc_crc_data1[0]) ^ main_rx_crc_crc_data1[6]); + main_rx_crc_crc_next[14] <= ((((((((((main_rx_crc_crc_last[6] ^ main_rx_crc_crc_last[31]) ^ main_rx_crc_crc_data1[0]) ^ main_rx_crc_crc_last[30]) ^ main_rx_crc_crc_data1[1]) ^ main_rx_crc_crc_last[28]) ^ main_rx_crc_crc_data1[3]) ^ main_rx_crc_crc_last[27]) ^ main_rx_crc_crc_data1[4]) ^ main_rx_crc_crc_last[26]) ^ main_rx_crc_crc_data1[5]); + main_rx_crc_crc_next[15] <= ((((((((main_rx_crc_crc_last[7] ^ main_rx_crc_crc_last[31]) ^ main_rx_crc_crc_data1[0]) ^ main_rx_crc_crc_last[29]) ^ main_rx_crc_crc_data1[2]) ^ main_rx_crc_crc_last[28]) ^ main_rx_crc_crc_data1[3]) ^ main_rx_crc_crc_last[27]) ^ main_rx_crc_crc_data1[4]); + main_rx_crc_crc_next[16] <= ((((((main_rx_crc_crc_last[8] ^ main_rx_crc_crc_last[29]) ^ main_rx_crc_crc_data1[2]) ^ main_rx_crc_crc_last[28]) ^ main_rx_crc_crc_data1[3]) ^ main_rx_crc_crc_last[24]) ^ main_rx_crc_crc_data1[7]); + main_rx_crc_crc_next[17] <= ((((((main_rx_crc_crc_last[9] ^ main_rx_crc_crc_last[30]) ^ main_rx_crc_crc_data1[1]) ^ main_rx_crc_crc_last[29]) ^ main_rx_crc_crc_data1[2]) ^ main_rx_crc_crc_last[25]) ^ main_rx_crc_crc_data1[6]); + main_rx_crc_crc_next[18] <= ((((((main_rx_crc_crc_last[10] ^ main_rx_crc_crc_last[31]) ^ main_rx_crc_crc_data1[0]) ^ main_rx_crc_crc_last[30]) ^ main_rx_crc_crc_data1[1]) ^ main_rx_crc_crc_last[26]) ^ main_rx_crc_crc_data1[5]); + main_rx_crc_crc_next[19] <= ((((main_rx_crc_crc_last[11] ^ main_rx_crc_crc_last[31]) ^ main_rx_crc_crc_data1[0]) ^ main_rx_crc_crc_last[27]) ^ main_rx_crc_crc_data1[4]); + main_rx_crc_crc_next[20] <= ((main_rx_crc_crc_last[12] ^ main_rx_crc_crc_last[28]) ^ main_rx_crc_crc_data1[3]); + main_rx_crc_crc_next[21] <= ((main_rx_crc_crc_last[13] ^ main_rx_crc_crc_last[29]) ^ main_rx_crc_crc_data1[2]); + main_rx_crc_crc_next[22] <= ((main_rx_crc_crc_last[14] ^ main_rx_crc_crc_last[24]) ^ main_rx_crc_crc_data1[7]); + main_rx_crc_crc_next[23] <= ((((((main_rx_crc_crc_last[15] ^ main_rx_crc_crc_last[25]) ^ main_rx_crc_crc_data1[6]) ^ main_rx_crc_crc_last[24]) ^ main_rx_crc_crc_last[30]) ^ main_rx_crc_crc_data1[1]) ^ main_rx_crc_crc_data1[7]); + main_rx_crc_crc_next[24] <= ((((((main_rx_crc_crc_last[16] ^ main_rx_crc_crc_last[26]) ^ main_rx_crc_crc_data1[5]) ^ main_rx_crc_crc_last[25]) ^ main_rx_crc_crc_last[31]) ^ main_rx_crc_crc_data1[0]) ^ main_rx_crc_crc_data1[6]); + main_rx_crc_crc_next[25] <= ((((main_rx_crc_crc_last[17] ^ main_rx_crc_crc_last[27]) ^ main_rx_crc_crc_data1[4]) ^ main_rx_crc_crc_last[26]) ^ main_rx_crc_crc_data1[5]); + main_rx_crc_crc_next[26] <= ((((((((main_rx_crc_crc_last[18] ^ main_rx_crc_crc_last[28]) ^ main_rx_crc_crc_data1[3]) ^ main_rx_crc_crc_last[27]) ^ main_rx_crc_crc_data1[4]) ^ main_rx_crc_crc_last[24]) ^ main_rx_crc_crc_last[30]) ^ main_rx_crc_crc_data1[1]) ^ main_rx_crc_crc_data1[7]); + main_rx_crc_crc_next[27] <= ((((((((main_rx_crc_crc_last[19] ^ main_rx_crc_crc_last[29]) ^ main_rx_crc_crc_data1[2]) ^ main_rx_crc_crc_last[28]) ^ main_rx_crc_crc_data1[3]) ^ main_rx_crc_crc_last[25]) ^ main_rx_crc_crc_last[31]) ^ main_rx_crc_crc_data1[0]) ^ main_rx_crc_crc_data1[6]); + main_rx_crc_crc_next[28] <= ((((((main_rx_crc_crc_last[20] ^ main_rx_crc_crc_last[30]) ^ main_rx_crc_crc_data1[1]) ^ main_rx_crc_crc_last[29]) ^ main_rx_crc_crc_data1[2]) ^ main_rx_crc_crc_last[26]) ^ main_rx_crc_crc_data1[5]); + main_rx_crc_crc_next[29] <= ((((((main_rx_crc_crc_last[21] ^ main_rx_crc_crc_last[31]) ^ main_rx_crc_crc_data1[0]) ^ main_rx_crc_crc_last[30]) ^ main_rx_crc_crc_data1[1]) ^ main_rx_crc_crc_last[27]) ^ main_rx_crc_crc_data1[4]); + main_rx_crc_crc_next[30] <= ((((main_rx_crc_crc_last[22] ^ main_rx_crc_crc_last[31]) ^ main_rx_crc_crc_data1[0]) ^ main_rx_crc_crc_last[28]) ^ main_rx_crc_crc_data1[3]); + main_rx_crc_crc_next[31] <= ((main_rx_crc_crc_last[23] ^ main_rx_crc_crc_last[29]) ^ main_rx_crc_crc_data1[2]); +end +assign main_rx_crc_syncfifo_syncfifo_din = {main_rx_crc_syncfifo_fifo_in_last, main_rx_crc_syncfifo_fifo_in_first, main_rx_crc_syncfifo_fifo_in_payload_error, main_rx_crc_syncfifo_fifo_in_payload_last_be, main_rx_crc_syncfifo_fifo_in_payload_data}; +assign {main_rx_crc_syncfifo_fifo_out_last, main_rx_crc_syncfifo_fifo_out_first, main_rx_crc_syncfifo_fifo_out_payload_error, main_rx_crc_syncfifo_fifo_out_payload_last_be, main_rx_crc_syncfifo_fifo_out_payload_data} = main_rx_crc_syncfifo_syncfifo_dout; +assign main_rx_crc_syncfifo_sink_ready = main_rx_crc_syncfifo_syncfifo_writable; +assign main_rx_crc_syncfifo_syncfifo_we = main_rx_crc_syncfifo_sink_valid; +assign main_rx_crc_syncfifo_fifo_in_first = main_rx_crc_syncfifo_sink_first; +assign main_rx_crc_syncfifo_fifo_in_last = main_rx_crc_syncfifo_sink_last; +assign main_rx_crc_syncfifo_fifo_in_payload_data = main_rx_crc_syncfifo_sink_payload_data; +assign main_rx_crc_syncfifo_fifo_in_payload_last_be = main_rx_crc_syncfifo_sink_payload_last_be; +assign main_rx_crc_syncfifo_fifo_in_payload_error = main_rx_crc_syncfifo_sink_payload_error; +assign main_rx_crc_syncfifo_source_valid = main_rx_crc_syncfifo_syncfifo_readable; +assign main_rx_crc_syncfifo_source_first = main_rx_crc_syncfifo_fifo_out_first; +assign main_rx_crc_syncfifo_source_last = main_rx_crc_syncfifo_fifo_out_last; +assign main_rx_crc_syncfifo_source_payload_data = main_rx_crc_syncfifo_fifo_out_payload_data; +assign main_rx_crc_syncfifo_source_payload_last_be = main_rx_crc_syncfifo_fifo_out_payload_last_be; +assign main_rx_crc_syncfifo_source_payload_error = main_rx_crc_syncfifo_fifo_out_payload_error; +assign main_rx_crc_syncfifo_syncfifo_re = main_rx_crc_syncfifo_source_ready; +always @(*) begin + main_rx_crc_syncfifo_wrport_adr <= 3'd0; + if (main_rx_crc_syncfifo_replace) begin + main_rx_crc_syncfifo_wrport_adr <= (main_rx_crc_syncfifo_produce - 1'd1); + end else begin + main_rx_crc_syncfifo_wrport_adr <= main_rx_crc_syncfifo_produce; + end +end +assign main_rx_crc_syncfifo_wrport_dat_w = main_rx_crc_syncfifo_syncfifo_din; +assign main_rx_crc_syncfifo_wrport_we = (main_rx_crc_syncfifo_syncfifo_we & (main_rx_crc_syncfifo_syncfifo_writable | main_rx_crc_syncfifo_replace)); +assign main_rx_crc_syncfifo_do_read = (main_rx_crc_syncfifo_syncfifo_readable & main_rx_crc_syncfifo_syncfifo_re); +assign main_rx_crc_syncfifo_rdport_adr = main_rx_crc_syncfifo_consume; +assign main_rx_crc_syncfifo_syncfifo_dout = main_rx_crc_syncfifo_rdport_dat_r; +assign main_rx_crc_syncfifo_syncfifo_writable = (main_rx_crc_syncfifo_level != 3'd5); +assign main_rx_crc_syncfifo_syncfifo_readable = (main_rx_crc_syncfifo_level != 1'd0); +always @(*) begin + builder_maccore_rxdatapath_bufferizeendpoints_next_state <= 2'd0; + main_rx_crc_fifo_reset <= 1'd0; + main_rx_crc_source_source_valid <= 1'd0; + main_rx_crc_crc_ce <= 1'd0; + main_rx_crc_last_be_next_value0 <= 1'd0; + main_rx_crc_crc_reset <= 1'd0; + main_rx_crc_source_source_last <= 1'd0; + main_rx_crc_last_be_next_value_ce0 <= 1'd0; + main_rx_crc_source_source_payload_data <= 8'd0; + main_rx_crc_crc_error1_next_value1 <= 1'd0; + main_rx_crc_source_source_payload_last_be <= 1'd0; + main_rx_crc_crc_error1_next_value_ce1 <= 1'd0; + main_rx_crc_source_source_payload_error <= 1'd0; + main_rx_crc_source_source_first <= 1'd0; + main_rx_crc_error <= 1'd0; + main_rx_crc_syncfifo_source_ready <= 1'd0; + builder_maccore_rxdatapath_bufferizeendpoints_next_state <= builder_maccore_rxdatapath_bufferizeendpoints_state; + case (builder_maccore_rxdatapath_bufferizeendpoints_state) + 1'd1: begin + if ((main_rx_crc_sink_sink_valid & main_rx_crc_sink_sink_ready)) begin + main_rx_crc_crc_ce <= 1'd1; + builder_maccore_rxdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + 2'd2: begin + main_rx_crc_syncfifo_source_ready <= main_rx_crc_fifo_out; + main_rx_crc_source_source_valid <= (main_rx_crc_sink_sink_valid & main_rx_crc_fifo_full); + main_rx_crc_source_source_payload_data <= main_rx_crc_syncfifo_source_payload_data; + main_rx_crc_source_source_payload_last_be <= main_rx_crc_syncfifo_source_payload_last_be; + main_rx_crc_source_source_payload_error <= main_rx_crc_syncfifo_source_payload_error; + if (1'd1) begin + main_rx_crc_source_source_last <= main_rx_crc_sink_sink_last; + main_rx_crc_source_source_payload_last_be <= main_rx_crc_sink_sink_payload_last_be; + end else begin + if ((main_rx_crc_sink_sink_payload_last_be & 4'd15)) begin + main_rx_crc_source_source_last <= main_rx_crc_sink_sink_last; + main_rx_crc_source_source_payload_last_be <= (main_rx_crc_sink_sink_payload_last_be <<< -3'd3); + end else begin + main_rx_crc_last_be_next_value0 <= (main_rx_crc_sink_sink_payload_last_be >>> 3'd4); + main_rx_crc_last_be_next_value_ce0 <= 1'd1; + main_rx_crc_crc_error1_next_value1 <= main_rx_crc_crc_error0; + main_rx_crc_crc_error1_next_value_ce1 <= 1'd1; + end + end + main_rx_crc_source_source_payload_error <= (main_rx_crc_sink_sink_payload_error | {1{(main_rx_crc_crc_error0 & main_rx_crc_sink_sink_last)}}); + main_rx_crc_error <= ((main_rx_crc_sink_sink_valid & main_rx_crc_sink_sink_last) & main_rx_crc_crc_error0); + if ((main_rx_crc_sink_sink_valid & main_rx_crc_sink_sink_ready)) begin + main_rx_crc_crc_ce <= 1'd1; + if ((main_rx_crc_sink_sink_last & (main_rx_crc_sink_sink_payload_last_be > 4'd15))) begin + builder_maccore_rxdatapath_bufferizeendpoints_next_state <= 2'd3; + end else begin + if (main_rx_crc_sink_sink_last) begin + builder_maccore_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + end + end + 2'd3: begin + main_rx_crc_source_source_valid <= main_rx_crc_syncfifo_source_valid; + main_rx_crc_syncfifo_source_ready <= main_rx_crc_source_source_ready; + main_rx_crc_source_source_first <= main_rx_crc_syncfifo_source_first; + main_rx_crc_source_source_last <= main_rx_crc_syncfifo_source_last; + main_rx_crc_source_source_payload_data <= main_rx_crc_syncfifo_source_payload_data; + main_rx_crc_source_source_payload_last_be <= main_rx_crc_syncfifo_source_payload_last_be; + main_rx_crc_source_source_payload_error <= main_rx_crc_syncfifo_source_payload_error; + main_rx_crc_source_source_payload_error <= (main_rx_crc_syncfifo_source_payload_error | {1{main_rx_crc_crc_error1}}); + main_rx_crc_source_source_payload_last_be <= main_rx_crc_last_be; + if ((main_rx_crc_source_source_valid & main_rx_crc_source_source_ready)) begin + builder_maccore_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + default: begin + main_rx_crc_crc_reset <= 1'd1; + main_rx_crc_fifo_reset <= 1'd1; + builder_maccore_rxdatapath_bufferizeendpoints_next_state <= 1'd1; + end + endcase +end +assign main_rx_crc_sink_ready = ((~main_rx_crc_source_valid) | main_rx_crc_source_ready); +assign main_pulsesynchronizer1_o = (main_pulsesynchronizer1_toggle_o ^ main_pulsesynchronizer1_toggle_o_r); +assign main_rx_padding_source_valid = main_rx_padding_sink_valid; +assign main_rx_padding_sink_ready = main_rx_padding_source_ready; +assign main_rx_padding_source_first = main_rx_padding_sink_first; +assign main_rx_padding_source_last = main_rx_padding_sink_last; +assign main_rx_padding_source_payload_data = main_rx_padding_sink_payload_data; +assign main_rx_padding_source_payload_last_be = main_rx_padding_sink_payload_last_be; +assign main_rx_padding_source_payload_error = main_rx_padding_sink_payload_error; +assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid; +assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready; +assign main_rx_last_be_source_first = main_rx_last_be_sink_first; +assign main_rx_last_be_source_last = main_rx_last_be_sink_last; +assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data; +assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error; +always @(*) begin + main_rx_last_be_source_payload_last_be <= 1'd0; + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; + if (1'd1) begin + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; + end +end +assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid; +assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first; +assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last; +assign main_rx_converter_sink_ready = main_rx_converter_converter_sink_ready; +assign main_rx_converter_converter_sink_payload_data = {main_rx_converter_sink_payload_error, main_rx_converter_sink_payload_last_be, main_rx_converter_sink_payload_data}; +assign main_rx_converter_source_valid = main_rx_converter_source_source_valid; +assign main_rx_converter_source_first = main_rx_converter_source_source_first; +assign main_rx_converter_source_last = main_rx_converter_source_source_last; +assign main_rx_converter_source_source_ready = main_rx_converter_source_ready; +always @(*) begin + main_rx_converter_source_payload_data <= 32'd0; + main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; + main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; + main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; + main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; +end +always @(*) begin + main_rx_converter_source_payload_last_be <= 4'd0; + main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; + main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; + main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; + main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; +end +always @(*) begin + main_rx_converter_source_payload_error <= 4'd0; + main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; + main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; + main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; + main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; +end +assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid; +assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready; +assign main_rx_converter_source_source_first = main_rx_converter_converter_source_first; +assign main_rx_converter_source_source_last = main_rx_converter_converter_source_last; +assign main_rx_converter_source_source_payload_data = main_rx_converter_converter_source_payload_data; +assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready); +assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all; +assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready); +assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid; +assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready; +assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first; +assign main_rx_cdc_cdc_sink_last = main_rx_cdc_sink_sink_last; +assign main_rx_cdc_cdc_sink_payload_data = main_rx_cdc_sink_sink_payload_data; +assign main_rx_cdc_cdc_sink_payload_last_be = main_rx_cdc_sink_sink_payload_last_be; +assign main_rx_cdc_cdc_sink_payload_error = main_rx_cdc_sink_sink_payload_error; +assign main_rx_cdc_source_source_valid = main_rx_cdc_cdc_source_valid; +assign main_rx_cdc_cdc_source_ready = main_rx_cdc_source_source_ready; +assign main_rx_cdc_source_source_first = main_rx_cdc_cdc_source_first; +assign main_rx_cdc_source_source_last = main_rx_cdc_cdc_source_last; +assign main_rx_cdc_source_source_payload_data = main_rx_cdc_cdc_source_payload_data; +assign main_rx_cdc_source_source_payload_last_be = main_rx_cdc_cdc_source_payload_last_be; +assign main_rx_cdc_source_source_payload_error = main_rx_cdc_cdc_source_payload_error; +assign main_rx_cdc_cdc_asyncfifo_din = {main_rx_cdc_cdc_fifo_in_last, main_rx_cdc_cdc_fifo_in_first, main_rx_cdc_cdc_fifo_in_payload_error, main_rx_cdc_cdc_fifo_in_payload_last_be, main_rx_cdc_cdc_fifo_in_payload_data}; +assign {main_rx_cdc_cdc_fifo_out_last, main_rx_cdc_cdc_fifo_out_first, main_rx_cdc_cdc_fifo_out_payload_error, main_rx_cdc_cdc_fifo_out_payload_last_be, main_rx_cdc_cdc_fifo_out_payload_data} = main_rx_cdc_cdc_asyncfifo_dout; +assign main_rx_cdc_cdc_sink_ready = main_rx_cdc_cdc_asyncfifo_writable; +assign main_rx_cdc_cdc_asyncfifo_we = main_rx_cdc_cdc_sink_valid; +assign main_rx_cdc_cdc_fifo_in_first = main_rx_cdc_cdc_sink_first; +assign main_rx_cdc_cdc_fifo_in_last = main_rx_cdc_cdc_sink_last; +assign main_rx_cdc_cdc_fifo_in_payload_data = main_rx_cdc_cdc_sink_payload_data; +assign main_rx_cdc_cdc_fifo_in_payload_last_be = main_rx_cdc_cdc_sink_payload_last_be; +assign main_rx_cdc_cdc_fifo_in_payload_error = main_rx_cdc_cdc_sink_payload_error; +assign main_rx_cdc_cdc_source_valid = main_rx_cdc_cdc_asyncfifo_readable; +assign main_rx_cdc_cdc_source_first = main_rx_cdc_cdc_fifo_out_first; +assign main_rx_cdc_cdc_source_last = main_rx_cdc_cdc_fifo_out_last; +assign main_rx_cdc_cdc_source_payload_data = main_rx_cdc_cdc_fifo_out_payload_data; +assign main_rx_cdc_cdc_source_payload_last_be = main_rx_cdc_cdc_fifo_out_payload_last_be; +assign main_rx_cdc_cdc_source_payload_error = main_rx_cdc_cdc_fifo_out_payload_error; +assign main_rx_cdc_cdc_asyncfifo_re = main_rx_cdc_cdc_source_ready; +assign main_rx_cdc_cdc_graycounter0_ce = (main_rx_cdc_cdc_asyncfifo_writable & main_rx_cdc_cdc_asyncfifo_we); +assign main_rx_cdc_cdc_graycounter1_ce = (main_rx_cdc_cdc_asyncfifo_readable & main_rx_cdc_cdc_asyncfifo_re); +assign main_rx_cdc_cdc_asyncfifo_writable = (((main_rx_cdc_cdc_graycounter0_q[5] == main_rx_cdc_cdc_consume_wdomain[5]) | (main_rx_cdc_cdc_graycounter0_q[4] == main_rx_cdc_cdc_consume_wdomain[4])) | (main_rx_cdc_cdc_graycounter0_q[3:0] != main_rx_cdc_cdc_consume_wdomain[3:0])); +assign main_rx_cdc_cdc_asyncfifo_readable = (main_rx_cdc_cdc_graycounter1_q != main_rx_cdc_cdc_produce_rdomain); +assign main_rx_cdc_cdc_wrport_adr = main_rx_cdc_cdc_graycounter0_q_binary[4:0]; +assign main_rx_cdc_cdc_wrport_dat_w = main_rx_cdc_cdc_asyncfifo_din; +assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce; +assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r; +always @(*) begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter0_ce) begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; + end +end +assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); +always @(*) begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter1_ce) begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; + end +end +assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign main_rx_preamble_sink_valid = main_maccore_ethphy_source_valid; +assign main_maccore_ethphy_source_ready = main_rx_preamble_sink_ready; +assign main_rx_preamble_sink_first = main_maccore_ethphy_source_first; +assign main_rx_preamble_sink_last = main_maccore_ethphy_source_last; +assign main_rx_preamble_sink_payload_data = main_maccore_ethphy_source_payload_data; +assign main_rx_preamble_sink_payload_last_be = main_maccore_ethphy_source_payload_last_be; +assign main_rx_preamble_sink_payload_error = main_maccore_ethphy_source_payload_error; +assign main_rx_crc_sink_valid = main_rx_preamble_source_valid; +assign main_rx_preamble_source_ready = main_rx_crc_sink_ready; +assign main_rx_crc_sink_first = main_rx_preamble_source_first; +assign main_rx_crc_sink_last = main_rx_preamble_source_last; +assign main_rx_crc_sink_payload_data = main_rx_preamble_source_payload_data; +assign main_rx_crc_sink_payload_last_be = main_rx_preamble_source_payload_last_be; +assign main_rx_crc_sink_payload_error = main_rx_preamble_source_payload_error; +assign main_rx_padding_sink_valid = main_rx_crc_source_source_valid; +assign main_rx_crc_source_source_ready = main_rx_padding_sink_ready; +assign main_rx_padding_sink_first = main_rx_crc_source_source_first; +assign main_rx_padding_sink_last = main_rx_crc_source_source_last; +assign main_rx_padding_sink_payload_data = main_rx_crc_source_source_payload_data; +assign main_rx_padding_sink_payload_last_be = main_rx_crc_source_source_payload_last_be; +assign main_rx_padding_sink_payload_error = main_rx_crc_source_source_payload_error; +assign main_rx_last_be_sink_valid = main_rx_padding_source_valid; +assign main_rx_padding_source_ready = main_rx_last_be_sink_ready; +assign main_rx_last_be_sink_first = main_rx_padding_source_first; +assign main_rx_last_be_sink_last = main_rx_padding_source_last; +assign main_rx_last_be_sink_payload_data = main_rx_padding_source_payload_data; +assign main_rx_last_be_sink_payload_last_be = main_rx_padding_source_payload_last_be; +assign main_rx_last_be_sink_payload_error = main_rx_padding_source_payload_error; +assign main_rx_converter_sink_valid = main_rx_last_be_source_valid; +assign main_rx_last_be_source_ready = main_rx_converter_sink_ready; +assign main_rx_converter_sink_first = main_rx_last_be_source_first; +assign main_rx_converter_sink_last = main_rx_last_be_source_last; +assign main_rx_converter_sink_payload_data = main_rx_last_be_source_payload_data; +assign main_rx_converter_sink_payload_last_be = main_rx_last_be_source_payload_last_be; +assign main_rx_converter_sink_payload_error = main_rx_last_be_source_payload_error; +assign main_rx_cdc_sink_sink_valid = main_rx_converter_source_valid; +assign main_rx_converter_source_ready = main_rx_cdc_sink_sink_ready; +assign main_rx_cdc_sink_sink_first = main_rx_converter_source_first; +assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last; +assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data; +assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be; +assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error; +assign main_source_valid = main_rx_cdc_source_source_valid; +assign main_rx_cdc_source_source_ready = main_source_ready; +assign main_source_first = main_rx_cdc_source_source_first; +assign main_source_last = main_rx_cdc_source_source_last; +assign main_source_payload_data = main_rx_cdc_source_source_payload_data; +assign main_source_payload_last_be = main_rx_cdc_source_source_payload_last_be; +assign main_source_payload_error = main_rx_cdc_source_source_payload_error; +assign main_sram0_sink_valid = main_sink_sink_valid; +assign main_sink_sink_ready = main_sram1_sink_ready; +assign main_sram2_sink_first = main_sink_sink_first; +assign main_sram3_sink_last = main_sink_sink_last; +assign main_sram4_sink_payload_data = main_sink_sink_payload_data; +assign main_sram5_sink_payload_last_be = main_sink_sink_payload_last_be; +assign main_sram6_sink_payload_error = main_sink_sink_payload_error; +assign main_source_source_valid = main_sram83_source_valid; +assign main_sram84_source_ready = main_source_source_ready; +assign main_source_source_first = main_sram85_source_first; +assign main_source_source_last = main_sram86_source_last; +assign main_source_source_payload_data = main_sram87_source_payload_data; +assign main_source_source_payload_last_be = main_sram88_source_payload_last_be; +assign main_source_source_payload_error = main_sram89_source_payload_error; +always @(*) begin + main_length_inc <= 4'd0; + case (main_sram5_sink_payload_last_be) + 1'd1: begin + main_length_inc <= 1'd1; + end + 2'd2: begin + main_length_inc <= 2'd2; + end + 3'd4: begin + main_length_inc <= 2'd3; + end + 4'd8: begin + main_length_inc <= 3'd4; + end + 5'd16: begin + main_length_inc <= 3'd5; + end + 6'd32: begin + main_length_inc <= 3'd6; + end + 7'd64: begin + main_length_inc <= 3'd7; + end + default: begin + main_length_inc <= 3'd4; + end + endcase +end +assign main_sram44_source_ready = main_sram20_clear; +assign main_sram19_trigger = main_sram43_source_valid; +assign main_sram7_status = main_sram47_source_payload_slot; +assign main_sram10_status = main_sram48_source_payload_length; +assign main_wr_data = main_sram4_sink_payload_data; +always @(*) begin + main_sram79_adr <= 9'd0; + main_sram81_we <= 1'd0; + main_sram75_adr <= 9'd0; + main_sram82_dat_w <= 32'd0; + main_sram77_we <= 1'd0; + main_sram78_dat_w <= 32'd0; + case (main_slot) + 1'd0: begin + main_sram75_adr <= main_sram35_length[10:2]; + main_sram78_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram77_we <= 1'd1; + end + end + 1'd1: begin + main_sram79_adr <= main_sram35_length[10:2]; + main_sram82_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram81_we <= 1'd1; + end + end + endcase +end +assign main_sram21_available = main_sram17_status; +assign main_sram25_available = main_sram18_pending; +always @(*) begin + main_sram20_clear <= 1'd0; + if ((main_sram28_re & main_sram29_r)) begin + main_sram20_clear <= 1'd1; + end +end +assign main_sram16_irq = (main_sram26_status & main_sram31_storage); +assign main_sram17_status = main_sram19_trigger; +assign main_sram18_pending = main_sram19_trigger; +assign main_sram53_din = {main_sram69_fifo_in_last, main_sram68_fifo_in_first, main_sram67_fifo_in_payload_length, main_sram66_fifo_in_payload_slot}; +assign {main_sram73_fifo_out_last, main_sram72_fifo_out_first, main_sram71_fifo_out_payload_length, main_sram70_fifo_out_payload_slot} = main_sram54_dout; +assign main_sram38_sink_ready = main_sram50_writable; +assign main_sram49_we = main_sram37_sink_valid; +assign main_sram68_fifo_in_first = main_sram39_sink_first; +assign main_sram69_fifo_in_last = main_sram40_sink_last; +assign main_sram66_fifo_in_payload_slot = main_sram41_sink_payload_slot; +assign main_sram67_fifo_in_payload_length = main_sram42_sink_payload_length; +assign main_sram43_source_valid = main_sram52_readable; +assign main_sram45_source_first = main_sram72_fifo_out_first; +assign main_sram46_source_last = main_sram73_fifo_out_last; +assign main_sram47_source_payload_slot = main_sram70_fifo_out_payload_slot; +assign main_sram48_source_payload_length = main_sram71_fifo_out_payload_length; +assign main_sram51_re = main_sram44_source_ready; +always @(*) begin + main_sram59_adr <= 1'd0; + if (main_sram56_replace) begin + main_sram59_adr <= (main_sram57_produce - 1'd1); + end else begin + main_sram59_adr <= main_sram57_produce; + end +end +assign main_sram62_dat_w = main_sram53_din; +assign main_sram61_we = (main_sram49_we & (main_sram50_writable | main_sram56_replace)); +assign main_sram63_do_read = (main_sram52_readable & main_sram51_re); +assign main_sram64_adr = main_sram58_consume; +assign main_sram54_dout = main_sram65_dat_r; +assign main_sram50_writable = (main_sram55_level != 2'd2); +assign main_sram52_readable = (main_sram55_level != 1'd0); +always @(*) begin + main_write <= 1'd0; + main_sram41_sink_payload_slot <= 1'd0; + main_sram42_sink_payload_length <= 11'd0; + main_slot_liteethmacsramwriter_next_value <= 1'd0; + main_slot_liteethmacsramwriter_next_value_ce <= 1'd0; + builder_maccore_liteethmacsramwriter_next_state <= 2'd0; + main_sram35_length_liteethmacsramwriter_t_next_value <= 11'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; + main_sram37_sink_valid <= 1'd0; + main_sram13_status_liteethmacsramwriter_f_next_value <= 32'd0; + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; + builder_maccore_liteethmacsramwriter_next_state <= builder_maccore_liteethmacsramwriter_state; + case (builder_maccore_liteethmacsramwriter_state) + 1'd1: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_maccore_liteethmacsramwriter_next_state <= 2'd2; + end else begin + builder_maccore_liteethmacsramwriter_next_state <= 2'd3; + end + end + end + 2'd2: begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_maccore_liteethmacsramwriter_next_state <= 1'd0; + end + 2'd3: begin + main_sram37_sink_valid <= 1'd1; + main_sram41_sink_payload_slot <= main_slot; + main_sram42_sink_payload_length <= main_sram35_length; + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + main_slot_liteethmacsramwriter_next_value <= (main_slot + 1'd1); + main_slot_liteethmacsramwriter_next_value_ce <= 1'd1; + builder_maccore_liteethmacsramwriter_next_state <= 1'd0; + end + default: begin + if (main_sram0_sink_valid) begin + if (main_sram38_sink_ready) begin + main_write <= 1'd1; + main_sram35_length_liteethmacsramwriter_t_next_value <= (main_sram35_length + main_length_inc); + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + if ((main_sram35_length >= 11'd1530)) begin + builder_maccore_liteethmacsramwriter_next_state <= 1'd1; + end + if (main_sram3_sink_last) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_maccore_liteethmacsramwriter_next_state <= 2'd2; + end else begin + builder_maccore_liteethmacsramwriter_next_state <= 2'd3; + end + end + end else begin + main_sram13_status_liteethmacsramwriter_f_next_value <= (main_sram13_status + 1'd1); + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; + builder_maccore_liteethmacsramwriter_next_state <= 1'd1; + end + end + end + endcase +end +assign main_sram123_sink_valid = main_start_re; +assign main_sram127_sink_payload_slot = main_sram100_storage; +assign main_sram128_sink_payload_length = main_sram102_storage; +assign main_sram94_status = main_sram124_sink_ready; +assign main_sram97_status = main_sram141_level; +always @(*) begin + main_sram88_source_payload_last_be <= 4'd0; + if (main_sram86_source_last) begin + case (main_sram134_source_payload_length[1:0]) + 1'd1: begin + main_sram88_source_payload_last_be <= 1'd1; + end + 2'd2: begin + main_sram88_source_payload_last_be <= 2'd2; + end + 2'd3: begin + main_sram88_source_payload_last_be <= 3'd4; + end + 3'd4: begin + main_sram88_source_payload_last_be <= 4'd8; + end + 3'd5: begin + main_sram88_source_payload_last_be <= 5'd16; + end + 3'd6: begin + main_sram88_source_payload_last_be <= 6'd32; + end + 3'd7: begin + main_sram88_source_payload_last_be <= 7'd64; + end + default: begin + main_sram88_source_payload_last_be <= 4'd8; + end + endcase + end +end +assign main_sram163_re = main_read; +assign main_sram161_adr = main_sram122_length[10:2]; +assign main_sram166_re = main_read; +assign main_sram164_adr = main_sram122_length[10:2]; +always @(*) begin + main_rd_data <= 32'd0; + case (main_sram133_source_payload_slot) + 1'd0: begin + main_rd_data <= main_sram162_dat_r; + end + 1'd1: begin + main_rd_data <= main_sram165_dat_r; + end + endcase +end +assign main_sram87_source_payload_data = main_rd_data; +assign main_sram109_event0 = main_sram105_status; +assign main_sram113_event0 = main_sram106_pending; +always @(*) begin + main_sram108_clear <= 1'd0; + if ((main_sram116_re & main_sram117_r)) begin + main_sram108_clear <= 1'd1; + end +end +assign main_sram104_irq = (main_sram114_status & main_sram119_storage); +assign main_sram105_status = 1'd0; +assign main_sram139_din = {main_sram155_fifo_in_last, main_sram154_fifo_in_first, main_sram153_fifo_in_payload_length, main_sram152_fifo_in_payload_slot}; +assign {main_sram159_fifo_out_last, main_sram158_fifo_out_first, main_sram157_fifo_out_payload_length, main_sram156_fifo_out_payload_slot} = main_sram140_dout; +assign main_sram124_sink_ready = main_sram136_writable; +assign main_sram135_we = main_sram123_sink_valid; +assign main_sram154_fifo_in_first = main_sram125_sink_first; +assign main_sram155_fifo_in_last = main_sram126_sink_last; +assign main_sram152_fifo_in_payload_slot = main_sram127_sink_payload_slot; +assign main_sram153_fifo_in_payload_length = main_sram128_sink_payload_length; +assign main_sram129_source_valid = main_sram138_readable; +assign main_sram131_source_first = main_sram158_fifo_out_first; +assign main_sram132_source_last = main_sram159_fifo_out_last; +assign main_sram133_source_payload_slot = main_sram156_fifo_out_payload_slot; +assign main_sram134_source_payload_length = main_sram157_fifo_out_payload_length; +assign main_sram137_re = main_sram130_source_ready; +always @(*) begin + main_sram145_adr <= 1'd0; + if (main_sram142_replace) begin + main_sram145_adr <= (main_sram143_produce - 1'd1); + end else begin + main_sram145_adr <= main_sram143_produce; + end +end +assign main_sram148_dat_w = main_sram139_din; +assign main_sram147_we = (main_sram135_we & (main_sram136_writable | main_sram142_replace)); +assign main_sram149_do_read = (main_sram138_readable & main_sram137_re); +assign main_sram150_adr = main_sram144_consume; +assign main_sram140_dout = main_sram151_dat_r; +assign main_sram136_writable = (main_sram141_level != 2'd2); +assign main_sram138_readable = (main_sram141_level != 1'd0); +always @(*) begin + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd0; + main_sram130_source_ready <= 1'd0; + main_sram86_source_last <= 1'd0; + main_sram107_trigger <= 1'd0; + main_sram83_source_valid <= 1'd0; + main_read <= 1'd0; + builder_maccore_liteethmacsramreader_next_state <= 2'd0; + main_sram122_length_liteethmacsramreader_next_value <= 11'd0; + builder_maccore_liteethmacsramreader_next_state <= builder_maccore_liteethmacsramreader_state; + case (builder_maccore_liteethmacsramreader_state) + 1'd1: begin + main_sram83_source_valid <= 1'd1; + main_sram86_source_last <= (main_sram122_length >= main_sram134_source_payload_length); + if (main_sram84_source_ready) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= (main_sram122_length + 3'd4); + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + if (main_sram86_source_last) begin + builder_maccore_liteethmacsramreader_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_sram122_length_liteethmacsramreader_next_value <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + main_sram107_trigger <= 1'd1; + main_sram130_source_ready <= 1'd1; + builder_maccore_liteethmacsramreader_next_state <= 1'd0; + end + default: begin + if (main_sram129_source_valid) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= 3'd4; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + builder_maccore_liteethmacsramreader_next_state <= 1'd1; + end + end + endcase +end +assign main_sram167_irq = (main_sram16_irq | main_sram104_irq); +assign main_sram0_adr = main_interface0_adr[8:0]; +assign main_interface0_dat_r = main_sram0_dat_r; +assign main_sram1_adr = main_interface1_adr[8:0]; +assign main_interface1_dat_r = main_sram1_dat_r; +always @(*) begin + main_sram2_we <= 4'd0; + main_sram2_we[0] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[0]); + main_sram2_we[1] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[1]); + main_sram2_we[2] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[2]); + main_sram2_we[3] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[3]); +end +assign main_sram2_adr = main_interface2_adr[8:0]; +assign main_interface2_dat_r = main_sram2_dat_r; +assign main_sram2_dat_w = main_interface2_dat_w; +always @(*) begin + main_sram3_we <= 4'd0; + main_sram3_we[0] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[0]); + main_sram3_we[1] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[1]); + main_sram3_we[2] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[2]); + main_sram3_we[3] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[3]); +end +assign main_sram3_adr = main_interface3_adr[8:0]; +assign main_interface3_dat_r = main_sram3_dat_r; +assign main_sram3_dat_w = main_interface3_dat_w; +always @(*) begin + main_slave_sel <= 4'd0; + main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); + main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); + main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); + main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); +end +assign main_interface0_adr = main_bus_adr; +assign main_interface0_dat_w = main_bus_dat_w; +assign main_interface0_sel = main_bus_sel; +assign main_interface0_stb = main_bus_stb; +assign main_interface0_we = main_bus_we; +assign main_interface0_cti = main_bus_cti; +assign main_interface0_bte = main_bus_bte; +assign main_interface1_adr = main_bus_adr; +assign main_interface1_dat_w = main_bus_dat_w; +assign main_interface1_sel = main_bus_sel; +assign main_interface1_stb = main_bus_stb; +assign main_interface1_we = main_bus_we; +assign main_interface1_cti = main_bus_cti; +assign main_interface1_bte = main_bus_bte; +assign main_interface2_adr = main_bus_adr; +assign main_interface2_dat_w = main_bus_dat_w; +assign main_interface2_sel = main_bus_sel; +assign main_interface2_stb = main_bus_stb; +assign main_interface2_we = main_bus_we; +assign main_interface2_cti = main_bus_cti; +assign main_interface2_bte = main_bus_bte; +assign main_interface3_adr = main_bus_adr; +assign main_interface3_dat_w = main_bus_dat_w; +assign main_interface3_sel = main_bus_sel; +assign main_interface3_stb = main_bus_stb; +assign main_interface3_we = main_bus_we; +assign main_interface3_cti = main_bus_cti; +assign main_interface3_bte = main_bus_bte; +assign main_interface0_cyc = (main_bus_cyc & main_slave_sel[0]); +assign main_interface1_cyc = (main_bus_cyc & main_slave_sel[1]); +assign main_interface2_cyc = (main_bus_cyc & main_slave_sel[2]); +assign main_interface3_cyc = (main_bus_cyc & main_slave_sel[3]); +assign main_bus_ack = (((main_interface0_ack | main_interface1_ack) | main_interface2_ack) | main_interface3_ack); +assign main_bus_err = (((main_interface0_err | main_interface1_err) | main_interface2_err) | main_interface3_err); +assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_interface0_dat_r) | ({32{main_slave_sel_r[1]}} & main_interface1_dat_r)) | ({32{main_slave_sel_r[2]}} & main_interface2_dat_r)) | ({32{main_slave_sel_r[3]}} & main_interface3_dat_r)); +always @(*) begin + builder_maccore_adr <= 14'd0; + builder_maccore_we <= 1'd0; + builder_maccore_next_state <= 1'd0; + builder_maccore_dat_w <= 32'd0; + builder_maccore_wishbone_ack <= 1'd0; + builder_maccore_wishbone_dat_r <= 32'd0; + builder_maccore_next_state <= builder_maccore_state; + case (builder_maccore_state) + 1'd1: begin + builder_maccore_wishbone_ack <= 1'd1; + builder_maccore_wishbone_dat_r <= builder_maccore_dat_r; + builder_maccore_next_state <= 1'd0; + end + default: begin + builder_maccore_dat_w <= builder_maccore_wishbone_dat_w; + if ((builder_maccore_wishbone_cyc & builder_maccore_wishbone_stb)) begin + builder_maccore_adr <= builder_maccore_wishbone_adr; + builder_maccore_we <= (builder_maccore_wishbone_we & (builder_maccore_wishbone_sel != 1'd0)); + builder_maccore_next_state <= 1'd1; + end + end + endcase +end +assign builder_shared_adr = builder_array_muxed0; +assign builder_shared_dat_w = builder_array_muxed1; +assign builder_shared_sel = builder_array_muxed2; +assign builder_shared_cyc = builder_array_muxed3; +assign builder_shared_stb = builder_array_muxed4; +assign builder_shared_we = builder_array_muxed5; +assign builder_shared_cti = builder_array_muxed6; +assign builder_shared_bte = builder_array_muxed7; +assign main_wb_bus_dat_r = builder_shared_dat_r; +assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); +assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); +assign builder_request = {main_wb_bus_cyc}; +assign builder_grant = 1'd0; +always @(*) begin + builder_slave_sel <= 2'd0; + builder_slave_sel[0] <= (builder_shared_adr[29:11] == 5'd16); + builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); +end +assign main_bus_adr = builder_shared_adr; +assign main_bus_dat_w = builder_shared_dat_w; +assign main_bus_sel = builder_shared_sel; +assign main_bus_stb = builder_shared_stb; +assign main_bus_we = builder_shared_we; +assign main_bus_cti = builder_shared_cti; +assign main_bus_bte = builder_shared_bte; +assign builder_maccore_wishbone_adr = builder_shared_adr; +assign builder_maccore_wishbone_dat_w = builder_shared_dat_w; +assign builder_maccore_wishbone_sel = builder_shared_sel; +assign builder_maccore_wishbone_stb = builder_shared_stb; +assign builder_maccore_wishbone_we = builder_shared_we; +assign builder_maccore_wishbone_cti = builder_shared_cti; +assign builder_maccore_wishbone_bte = builder_shared_bte; +assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); +assign builder_maccore_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[1]); +assign builder_shared_err = (main_bus_err | builder_maccore_wishbone_err); +assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +always @(*) begin + builder_shared_dat_r <= 32'd0; + builder_shared_ack <= 1'd0; + builder_error <= 1'd0; + builder_shared_ack <= (main_bus_ack | builder_maccore_wishbone_ack); + builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_maccore_wishbone_dat_r)); + if (builder_done) begin + builder_shared_dat_r <= 32'd4294967295; + builder_shared_ack <= 1'd1; + builder_error <= 1'd1; + end +end +assign builder_done = (builder_count == 1'd0); +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csrbank0_reset0_re <= 1'd0; + builder_csrbank0_reset0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); + end +end +assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank0_scratch0_we <= 1'd0; + builder_csrbank0_scratch0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); + end +end +assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank0_bus_errors_re <= 1'd0; + builder_csrbank0_bus_errors_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; + builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); + end +end +always @(*) begin + main_maccore_maccore_soc_rst <= 1'd0; + if (main_maccore_maccore_reset_re) begin + main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0]; + end +end +assign main_maccore_maccore_cpu_rst = main_maccore_maccore_reset_storage[1]; +assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage[1:0]; +assign builder_csrbank0_scratch0_w = main_maccore_maccore_scratch_storage[31:0]; +assign builder_csrbank0_bus_errors_w = main_maccore_maccore_bus_errors_status[31:0]; +assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_slot_we <= 1'd0; + builder_csrbank1_sram_writer_slot_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[10:0]; +always @(*) begin + builder_csrbank1_sram_writer_length_re <= 1'd0; + builder_csrbank1_sram_writer_length_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_sram_writer_errors_re <= 1'd0; + builder_csrbank1_sram_writer_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_ev_status_we <= 1'd0; + builder_csrbank1_sram_writer_ev_status_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; + builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end +end +assign main_start_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + main_start_we <= 1'd0; + main_start_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_start_re <= builder_interface1_bank_bus_we; + main_start_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ready_we <= 1'd0; + builder_csrbank1_sram_reader_ready_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csrbank1_sram_reader_level_we <= 1'd0; + builder_csrbank1_sram_reader_level_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_slot0_re <= 1'd0; + builder_csrbank1_sram_reader_slot0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0]; +always @(*) begin + builder_csrbank1_sram_reader_length0_we <= 1'd0; + builder_csrbank1_sram_reader_length0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ev_status_we <= 1'd0; + builder_csrbank1_sram_reader_ev_status_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; + builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; + builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_preamble_crc_we <= 1'd0; + builder_csrbank1_preamble_crc_re <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; + builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_preamble_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_preamble_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_crc_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_crc_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank1_rx_datapath_crc_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_crc_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_slot_w = main_sram7_status; +assign main_sram8_we = builder_csrbank1_sram_writer_slot_we; +assign builder_csrbank1_sram_writer_length_w = main_sram10_status[10:0]; +assign main_sram11_we = builder_csrbank1_sram_writer_length_we; +assign builder_csrbank1_sram_writer_errors_w = main_sram13_status[31:0]; +assign main_sram14_we = builder_csrbank1_sram_writer_errors_we; +assign main_sram22_status = main_sram21_available; +assign builder_csrbank1_sram_writer_ev_status_w = main_sram22_status; +assign main_sram23_we = builder_csrbank1_sram_writer_ev_status_we; +assign main_sram26_status = main_sram25_available; +assign builder_csrbank1_sram_writer_ev_pending_w = main_sram26_status; +assign main_sram27_we = builder_csrbank1_sram_writer_ev_pending_we; +assign main_sram30_available = main_sram31_storage; +assign builder_csrbank1_sram_writer_ev_enable0_w = main_sram31_storage; +assign builder_csrbank1_sram_reader_ready_w = main_sram94_status; +assign main_sram95_we = builder_csrbank1_sram_reader_ready_we; +assign builder_csrbank1_sram_reader_level_w = main_sram97_status[1:0]; +assign main_sram98_we = builder_csrbank1_sram_reader_level_we; +assign builder_csrbank1_sram_reader_slot0_w = main_sram100_storage; +assign builder_csrbank1_sram_reader_length0_w = main_sram102_storage[10:0]; +assign main_sram110_status = main_sram109_event0; +assign builder_csrbank1_sram_reader_ev_status_w = main_sram110_status; +assign main_sram111_we = builder_csrbank1_sram_reader_ev_status_we; +assign main_sram114_status = main_sram113_event0; +assign builder_csrbank1_sram_reader_ev_pending_w = main_sram114_status; +assign main_sram115_we = builder_csrbank1_sram_reader_ev_pending_we; +assign main_sram118_event0 = main_sram119_storage; +assign builder_csrbank1_sram_reader_ev_enable0_w = main_sram119_storage; +assign builder_csrbank1_preamble_crc_w = main_status; +assign main_we = builder_csrbank1_preamble_crc_we; +assign builder_csrbank1_rx_datapath_preamble_errors_w = main_preamble_errors_status[31:0]; +assign main_preamble_errors_we = builder_csrbank1_rx_datapath_preamble_errors_we; +assign builder_csrbank1_rx_datapath_crc_errors_w = main_crc_errors_status[31:0]; +assign main_crc_errors_we = builder_csrbank1_rx_datapath_crc_errors_we; +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank2_crg_reset0_re <= 1'd0; + builder_csrbank2_crg_reset0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_rx_inband_status_r = builder_interface2_bank_bus_dat_w[2:0]; +always @(*) begin + builder_csrbank2_rx_inband_status_we <= 1'd0; + builder_csrbank2_rx_inband_status_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_rx_inband_status_re <= builder_interface2_bank_bus_we; + builder_csrbank2_rx_inband_status_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0]; +always @(*) begin + builder_csrbank2_mdio_w0_re <= 1'd0; + builder_csrbank2_mdio_w0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank2_mdio_r_re <= 1'd0; + builder_csrbank2_mdio_r_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage; +always @(*) begin + main_maccore_ethphy_status <= 3'd0; + main_maccore_ethphy_status[0] <= main_maccore_ethphy_link_status; + main_maccore_ethphy_status[1] <= main_maccore_ethphy_clock_speed; + main_maccore_ethphy_status[2] <= main_maccore_ethphy_duplex_status; +end +assign builder_csrbank2_rx_inband_status_w = main_maccore_ethphy_status[2:0]; +assign main_maccore_ethphy_we = builder_csrbank2_rx_inband_status_we; +assign main_maccore_ethphy_mdc = main_maccore_ethphy__w_storage[0]; +assign main_maccore_ethphy_oe = main_maccore_ethphy__w_storage[1]; +assign main_maccore_ethphy_w = main_maccore_ethphy__w_storage[2]; +assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy__w_storage[2:0]; +assign builder_csrbank2_mdio_r_w = main_maccore_ethphy__r_status; +assign main_maccore_ethphy__r_we = builder_csrbank2_mdio_r_we; +assign builder_csr_interconnect_adr = builder_maccore_adr; +assign builder_csr_interconnect_we = builder_maccore_we; +assign builder_csr_interconnect_dat_w = builder_maccore_dat_w; +assign builder_maccore_dat_r = builder_csr_interconnect_dat_r; +assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_interface0_bank_bus_we = builder_csr_interconnect_we; +assign builder_interface1_bank_bus_we = builder_csr_interconnect_we; +assign builder_interface2_bank_bus_we = builder_csr_interconnect_we; +assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); +assign builder_t_slice_proxy0 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy1 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy2 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy3 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy4 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy5 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy6 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy7 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy8 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy9 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy10 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy11 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy12 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy13 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy14 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy15 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy16 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy17 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy18 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy19 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy20 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy21 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy22 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy23 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy24 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy25 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy26 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy27 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy28 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy29 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy30 = (~main_liteethmaccrc32inserter_next); +assign builder_t_slice_proxy31 = (~main_liteethmaccrc32inserter_next); +assign builder_cases_slice_proxy = {main_liteethmaccrc32inserter_value, main_liteethmaccrc32inserter_sink_payload_data[7:0]}; +assign builder_t_slice_proxy32 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy33 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy34 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy35 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy36 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy37 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy38 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy39 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy40 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy41 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy42 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy43 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy44 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy45 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy46 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy47 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy48 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy49 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy50 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy51 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy52 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy53 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy54 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy55 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy56 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy57 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy58 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy59 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy60 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy61 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy62 = (~main_rx_crc_crc_next); +assign builder_t_slice_proxy63 = (~main_rx_crc_crc_next); +always @(*) begin + builder_array_muxed0 <= 30'd0; + case (builder_grant) + default: begin + builder_array_muxed0 <= main_wb_bus_adr; + end + endcase +end +always @(*) begin + builder_array_muxed1 <= 32'd0; + case (builder_grant) + default: begin + builder_array_muxed1 <= main_wb_bus_dat_w; + end + endcase +end +always @(*) begin + builder_array_muxed2 <= 4'd0; + case (builder_grant) + default: begin + builder_array_muxed2 <= main_wb_bus_sel; + end + endcase +end +always @(*) begin + builder_array_muxed3 <= 1'd0; + case (builder_grant) + default: begin + builder_array_muxed3 <= main_wb_bus_cyc; + end + endcase +end +always @(*) begin + builder_array_muxed4 <= 1'd0; + case (builder_grant) + default: begin + builder_array_muxed4 <= main_wb_bus_stb; + end + endcase +end +always @(*) begin + builder_array_muxed5 <= 1'd0; + case (builder_grant) + default: begin + builder_array_muxed5 <= main_wb_bus_we; + end + endcase +end +always @(*) begin + builder_array_muxed6 <= 3'd0; + case (builder_grant) + default: begin + builder_array_muxed6 <= main_wb_bus_cti; + end + endcase +end +always @(*) begin + builder_array_muxed7 <= 2'd0; + case (builder_grant) + default: begin + builder_array_muxed7 <= main_wb_bus_bte; + end + endcase +end +always @(*) begin + main_maccore_ethphy__r_status <= 1'd0; + main_maccore_ethphy__r_status <= main_maccore_ethphy_r; + main_maccore_ethphy__r_status <= builder_multiregimpl0_regs1; +end +assign main_tx_cdc_cdc_produce_rdomain = builder_multiregimpl1_regs1; +assign main_tx_cdc_cdc_consume_wdomain = builder_multiregimpl2_regs1; +assign main_pulsesynchronizer0_toggle_o = builder_multiregimpl3_regs1; +assign main_pulsesynchronizer1_toggle_o = builder_multiregimpl4_regs1; +assign main_rx_cdc_cdc_produce_rdomain = builder_multiregimpl5_regs1; +assign main_rx_cdc_cdc_consume_wdomain = builder_multiregimpl6_regs1; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge eth_rx_clk) begin + main_maccore_ethphy_rx_ctl_reg <= main_maccore_ethphy_rx_ctl; + main_maccore_ethphy_rx_data_reg <= main_maccore_ethphy_rx_data; + main_maccore_ethphy_rx_ctl_reg_d <= main_maccore_ethphy_rx_ctl_reg; + main_maccore_ethphy_source_valid <= main_maccore_ethphy_rx_ctl_reg[0]; + main_maccore_ethphy_source_payload_data <= main_maccore_ethphy_rx_data_reg; + if ((main_maccore_ethphy_rx_ctl == 1'd0)) begin + main_maccore_ethphy_link_status <= main_maccore_ethphy_rx_data[0]; + main_maccore_ethphy_clock_speed <= main_maccore_ethphy_rx_data[2:1]; + main_maccore_ethphy_duplex_status <= main_maccore_ethphy_rx_data[3]; + end + builder_maccore_rxdatapath_liteethmacpreamblechecker_state <= builder_maccore_rxdatapath_liteethmacpreamblechecker_next_state; + if (main_pulsesynchronizer0_i) begin + main_pulsesynchronizer0_toggle_i <= (~main_pulsesynchronizer0_toggle_i); + end + if (main_rx_crc_crc_ce) begin + main_rx_crc_crc_reg <= main_rx_crc_crc_next; + end + if (main_rx_crc_crc_reset) begin + main_rx_crc_crc_reg <= 32'd4294967295; + end + if (((main_rx_crc_syncfifo_syncfifo_we & main_rx_crc_syncfifo_syncfifo_writable) & (~main_rx_crc_syncfifo_replace))) begin + if ((main_rx_crc_syncfifo_produce == 3'd4)) begin + main_rx_crc_syncfifo_produce <= 1'd0; + end else begin + main_rx_crc_syncfifo_produce <= (main_rx_crc_syncfifo_produce + 1'd1); + end + end + if (main_rx_crc_syncfifo_do_read) begin + if ((main_rx_crc_syncfifo_consume == 3'd4)) begin + main_rx_crc_syncfifo_consume <= 1'd0; + end else begin + main_rx_crc_syncfifo_consume <= (main_rx_crc_syncfifo_consume + 1'd1); + end + end + if (((main_rx_crc_syncfifo_syncfifo_we & main_rx_crc_syncfifo_syncfifo_writable) & (~main_rx_crc_syncfifo_replace))) begin + if ((~main_rx_crc_syncfifo_do_read)) begin + main_rx_crc_syncfifo_level <= (main_rx_crc_syncfifo_level + 1'd1); + end + end else begin + if (main_rx_crc_syncfifo_do_read) begin + main_rx_crc_syncfifo_level <= (main_rx_crc_syncfifo_level - 1'd1); + end + end + if (main_rx_crc_fifo_reset) begin + main_rx_crc_syncfifo_level <= 3'd0; + main_rx_crc_syncfifo_produce <= 3'd0; + main_rx_crc_syncfifo_consume <= 3'd0; + end + builder_maccore_rxdatapath_bufferizeendpoints_state <= builder_maccore_rxdatapath_bufferizeendpoints_next_state; + if (main_rx_crc_last_be_next_value_ce0) begin + main_rx_crc_last_be <= main_rx_crc_last_be_next_value0; + end + if (main_rx_crc_crc_error1_next_value_ce1) begin + main_rx_crc_crc_error1 <= main_rx_crc_crc_error1_next_value1; + end + if (((~main_rx_crc_source_valid) | main_rx_crc_source_ready)) begin + main_rx_crc_source_valid <= main_rx_crc_sink_valid; + main_rx_crc_source_first <= main_rx_crc_sink_first; + main_rx_crc_source_last <= main_rx_crc_sink_last; + main_rx_crc_source_payload_data <= main_rx_crc_sink_payload_data; + main_rx_crc_source_payload_last_be <= main_rx_crc_sink_payload_last_be; + main_rx_crc_source_payload_error <= main_rx_crc_sink_payload_error; + end + if (main_pulsesynchronizer1_i) begin + main_pulsesynchronizer1_toggle_i <= (~main_pulsesynchronizer1_toggle_i); + end + if (main_rx_converter_converter_source_ready) begin + main_rx_converter_converter_strobe_all <= 1'd0; + end + if (main_rx_converter_converter_load_part) begin + if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin + main_rx_converter_converter_demux <= 1'd0; + main_rx_converter_converter_strobe_all <= 1'd1; + end else begin + main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); + end + end + if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; + main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; + end else begin + main_rx_converter_converter_source_first <= 1'd0; + main_rx_converter_converter_source_last <= 1'd0; + end + end else begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); + main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); + end + end + if (main_rx_converter_converter_load_part) begin + case (main_rx_converter_converter_demux) + 1'd0: begin + main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; + end + 1'd1: begin + main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; + end + 2'd2: begin + main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; + end + 2'd3: begin + main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; + end + endcase + end + if (main_rx_converter_converter_load_part) begin + main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); + end + main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; + main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; + if (eth_rx_rst) begin + main_maccore_ethphy_source_valid <= 1'd0; + main_maccore_ethphy_source_payload_data <= 8'd0; + main_maccore_ethphy_link_status <= 1'd0; + main_maccore_ethphy_clock_speed <= 1'd0; + main_maccore_ethphy_duplex_status <= 1'd0; + main_maccore_ethphy_rx_ctl_reg <= 2'd0; + main_maccore_ethphy_rx_data_reg <= 8'd0; + main_maccore_ethphy_rx_ctl_reg_d <= 2'd0; + main_rx_crc_crc_reg <= 32'd4294967295; + main_rx_crc_syncfifo_level <= 3'd0; + main_rx_crc_syncfifo_produce <= 3'd0; + main_rx_crc_syncfifo_consume <= 3'd0; + main_rx_crc_last_be <= 1'd0; + main_rx_crc_crc_error1 <= 1'd0; + main_rx_crc_source_valid <= 1'd0; + main_rx_crc_source_payload_data <= 8'd0; + main_rx_crc_source_payload_last_be <= 1'd0; + main_rx_crc_source_payload_error <= 1'd0; + main_rx_converter_converter_source_payload_data <= 40'd0; + main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; + main_rx_converter_converter_demux <= 2'd0; + main_rx_converter_converter_strobe_all <= 1'd0; + main_rx_cdc_cdc_graycounter0_q <= 6'd0; + main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; + builder_maccore_rxdatapath_liteethmacpreamblechecker_state <= 1'd0; + builder_maccore_rxdatapath_bufferizeendpoints_state <= 2'd0; + end + builder_multiregimpl6_regs0 <= main_rx_cdc_cdc_graycounter1_q; + builder_multiregimpl6_regs1 <= builder_multiregimpl6_regs0; +end + +always @(posedge eth_tx_clk) begin + main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; + main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; + if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin + if (main_tx_converter_converter_last) begin + main_tx_converter_converter_mux <= 1'd0; + end else begin + main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); + end + end + builder_maccore_txdatapath_liteethmactxlastbe_state <= builder_maccore_txdatapath_liteethmactxlastbe_next_state; + builder_maccore_txdatapath_liteethmacpaddinginserter_state <= builder_maccore_txdatapath_liteethmacpaddinginserter_next_state; + if (main_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin + main_tx_padding_counter <= main_tx_padding_counter_clockdomainsrenamer0_next_value; + end + if (main_liteethmaccrc32inserter_is_ongoing0) begin + main_liteethmaccrc32inserter_cnt <= 2'd3; + end else begin + if ((main_liteethmaccrc32inserter_is_ongoing1 & (~main_liteethmaccrc32inserter_cnt_done))) begin + main_liteethmaccrc32inserter_cnt <= (main_liteethmaccrc32inserter_cnt - main_liteethmaccrc32inserter_source_ready); + end + end + if (main_liteethmaccrc32inserter_ce) begin + main_liteethmaccrc32inserter_reg <= main_liteethmaccrc32inserter_next; + end + if (main_liteethmaccrc32inserter_reset) begin + main_liteethmaccrc32inserter_reg <= 32'd4294967295; + end + builder_maccore_txdatapath_bufferizeendpoints_state <= builder_maccore_txdatapath_bufferizeendpoints_next_state; + if (main_liteethmaccrc32inserter_crc_packet_clockdomainsrenamer1_next_value_ce0) begin + main_liteethmaccrc32inserter_crc_packet <= main_liteethmaccrc32inserter_crc_packet_clockdomainsrenamer1_next_value0; + end + if (main_liteethmaccrc32inserter_last_be2_clockdomainsrenamer1_next_value_ce1) begin + main_liteethmaccrc32inserter_last_be2 <= main_liteethmaccrc32inserter_last_be2_clockdomainsrenamer1_next_value1; + end + if (((~main_bufferizeendpoints_source_valid) | main_bufferizeendpoints_source_ready)) begin + main_bufferizeendpoints_source_valid <= main_bufferizeendpoints_sink_valid; + main_bufferizeendpoints_source_first <= main_bufferizeendpoints_sink_first; + main_bufferizeendpoints_source_last <= main_bufferizeendpoints_sink_last; + main_bufferizeendpoints_source_payload_data <= main_bufferizeendpoints_sink_payload_data; + main_bufferizeendpoints_source_payload_last_be <= main_bufferizeendpoints_sink_payload_last_be; + main_bufferizeendpoints_source_payload_error <= main_bufferizeendpoints_sink_payload_error; + end + builder_maccore_txdatapath_liteethmacpreambleinserter_state <= builder_maccore_txdatapath_liteethmacpreambleinserter_next_state; + if (main_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin + main_tx_preamble_count <= main_tx_preamble_count_clockdomainsrenamer2_next_value; + end + builder_maccore_txdatapath_liteethmacgap_state <= builder_maccore_txdatapath_liteethmacgap_next_state; + if (main_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin + main_tx_gap_counter <= main_tx_gap_counter_clockdomainsrenamer3_next_value; + end + if (eth_tx_rst) begin + main_tx_cdc_cdc_graycounter1_q <= 6'd0; + main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_tx_converter_converter_mux <= 2'd0; + main_tx_padding_counter <= 16'd0; + main_liteethmaccrc32inserter_reg <= 32'd4294967295; + main_liteethmaccrc32inserter_crc_packet <= 32'd0; + main_liteethmaccrc32inserter_last_be2 <= 1'd0; + main_liteethmaccrc32inserter_cnt <= 2'd3; + main_bufferizeendpoints_source_valid <= 1'd0; + main_bufferizeendpoints_source_payload_data <= 8'd0; + main_bufferizeendpoints_source_payload_last_be <= 1'd0; + main_bufferizeendpoints_source_payload_error <= 1'd0; + builder_maccore_txdatapath_liteethmactxlastbe_state <= 1'd0; + builder_maccore_txdatapath_liteethmacpaddinginserter_state <= 1'd0; + builder_maccore_txdatapath_bufferizeendpoints_state <= 2'd0; + builder_maccore_txdatapath_liteethmacpreambleinserter_state <= 2'd0; + builder_maccore_txdatapath_liteethmacgap_state <= 1'd0; + end + builder_multiregimpl1_regs0 <= main_tx_cdc_cdc_graycounter0_q; + builder_multiregimpl1_regs1 <= builder_multiregimpl1_regs0; +end + +always @(posedge por_clk) begin + main_maccore_int_rst <= sys_reset; +end + +always @(posedge sys_clk) begin + if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin + if (main_maccore_maccore_bus_error) begin + main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); + end + end + main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; + main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; + if (main_pulsesynchronizer0_o) begin + main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); + end + if (main_pulsesynchronizer1_o) begin + main_crc_errors_status <= (main_crc_errors_status + 1'd1); + end + main_pulsesynchronizer0_toggle_o_r <= main_pulsesynchronizer0_toggle_o; + main_pulsesynchronizer1_toggle_o_r <= main_pulsesynchronizer1_toggle_o; + main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; + main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + main_sram57_produce <= (main_sram57_produce + 1'd1); + end + if (main_sram63_do_read) begin + main_sram58_consume <= (main_sram58_consume + 1'd1); + end + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + if ((~main_sram63_do_read)) begin + main_sram55_level <= (main_sram55_level + 1'd1); + end + end else begin + if (main_sram63_do_read) begin + main_sram55_level <= (main_sram55_level - 1'd1); + end + end + builder_maccore_liteethmacsramwriter_state <= builder_maccore_liteethmacsramwriter_next_state; + if (main_sram35_length_liteethmacsramwriter_t_next_value_ce) begin + main_sram35_length <= main_sram35_length_liteethmacsramwriter_t_next_value; + end + if (main_sram13_status_liteethmacsramwriter_f_next_value_ce) begin + main_sram13_status <= main_sram13_status_liteethmacsramwriter_f_next_value; + end + if (main_slot_liteethmacsramwriter_next_value_ce) begin + main_slot <= main_slot_liteethmacsramwriter_next_value; + end + if (main_sram108_clear) begin + main_sram106_pending <= 1'd0; + end + if (main_sram107_trigger) begin + main_sram106_pending <= 1'd1; + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + main_sram143_produce <= (main_sram143_produce + 1'd1); + end + if (main_sram149_do_read) begin + main_sram144_consume <= (main_sram144_consume + 1'd1); + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + if ((~main_sram149_do_read)) begin + main_sram141_level <= (main_sram141_level + 1'd1); + end + end else begin + if (main_sram149_do_read) begin + main_sram141_level <= (main_sram141_level - 1'd1); + end + end + builder_maccore_liteethmacsramreader_state <= builder_maccore_liteethmacsramreader_next_state; + if (main_sram122_length_liteethmacsramreader_next_value_ce) begin + main_sram122_length <= main_sram122_length_liteethmacsramreader_next_value; + end + main_interface0_ack <= 1'd0; + if (((main_interface0_cyc & main_interface0_stb) & ((~main_interface0_ack) | main_sram0_adr_burst))) begin + main_interface0_ack <= 1'd1; + end + main_interface1_ack <= 1'd0; + if (((main_interface1_cyc & main_interface1_stb) & ((~main_interface1_ack) | main_sram1_adr_burst))) begin + main_interface1_ack <= 1'd1; + end + main_interface2_ack <= 1'd0; + if (((main_interface2_cyc & main_interface2_stb) & ((~main_interface2_ack) | main_sram2_adr_burst))) begin + main_interface2_ack <= 1'd1; + end + main_interface3_ack <= 1'd0; + if (((main_interface3_cyc & main_interface3_stb) & ((~main_interface3_ack) | main_sram3_adr_burst))) begin + main_interface3_ack <= 1'd1; + end + main_slave_sel_r <= main_slave_sel; + builder_maccore_state <= builder_maccore_next_state; + builder_slave_sel_r <= builder_slave_sel; + if (builder_wait) begin + if ((~builder_done)) begin + builder_count <= (builder_count - 1'd1); + end + end else begin + builder_count <= 20'd1000000; + end + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; + end + 1'd1: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; + end + 2'd2: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; + end + endcase + end + if (builder_csrbank0_reset0_re) begin + main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; + end + main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; + if (builder_csrbank0_scratch0_re) begin + main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; + end + main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; + main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; + end + 1'd1: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; + end + 2'd2: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; + end + 2'd3: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; + end + 3'd4: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; + end + 3'd5: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; + end + 3'd6: begin + builder_interface1_bank_bus_dat_r <= main_start_w; + end + 3'd7: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; + end + 4'd8: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; + end + 4'd9: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; + end + 4'd10: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; + end + 4'd11: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; + end + 4'd12: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; + end + 4'd13: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; + end + 4'd14: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; + end + 4'd15: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_preamble_errors_w; + end + 5'd16: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_crc_errors_w; + end + endcase + end + main_sram9_re <= builder_csrbank1_sram_writer_slot_re; + main_sram12_re <= builder_csrbank1_sram_writer_length_re; + main_sram15_re <= builder_csrbank1_sram_writer_errors_re; + main_sram24_re <= builder_csrbank1_sram_writer_ev_status_re; + if (builder_csrbank1_sram_writer_ev_pending_re) begin + main_sram29_r <= builder_csrbank1_sram_writer_ev_pending_r; + end + main_sram28_re <= builder_csrbank1_sram_writer_ev_pending_re; + if (builder_csrbank1_sram_writer_ev_enable0_re) begin + main_sram31_storage <= builder_csrbank1_sram_writer_ev_enable0_r; + end + main_sram32_re <= builder_csrbank1_sram_writer_ev_enable0_re; + main_sram96_re <= builder_csrbank1_sram_reader_ready_re; + main_sram99_re <= builder_csrbank1_sram_reader_level_re; + if (builder_csrbank1_sram_reader_slot0_re) begin + main_sram100_storage <= builder_csrbank1_sram_reader_slot0_r; + end + main_sram101_re <= builder_csrbank1_sram_reader_slot0_re; + if (builder_csrbank1_sram_reader_length0_re) begin + main_sram102_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; + end + main_sram103_re <= builder_csrbank1_sram_reader_length0_re; + main_sram112_re <= builder_csrbank1_sram_reader_ev_status_re; + if (builder_csrbank1_sram_reader_ev_pending_re) begin + main_sram117_r <= builder_csrbank1_sram_reader_ev_pending_r; + end + main_sram116_re <= builder_csrbank1_sram_reader_ev_pending_re; + if (builder_csrbank1_sram_reader_ev_enable0_re) begin + main_sram119_storage <= builder_csrbank1_sram_reader_ev_enable0_r; + end + main_sram120_re <= builder_csrbank1_sram_reader_ev_enable0_re; + main_re <= builder_csrbank1_preamble_crc_re; + main_preamble_errors_re <= builder_csrbank1_rx_datapath_preamble_errors_re; + main_crc_errors_re <= builder_csrbank1_rx_datapath_crc_errors_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; + end + 1'd1: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_rx_inband_status_w; + end + 2'd2: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; + end + 2'd3: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; + end + endcase + end + if (builder_csrbank2_crg_reset0_re) begin + main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; + end + main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; + main_maccore_ethphy_re <= builder_csrbank2_rx_inband_status_re; + if (builder_csrbank2_mdio_w0_re) begin + main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; + end + main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re; + main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re; + if (sys_rst) begin + main_maccore_maccore_reset_storage <= 2'd0; + main_maccore_maccore_reset_re <= 1'd0; + main_maccore_maccore_scratch_storage <= 32'd305419896; + main_maccore_maccore_scratch_re <= 1'd0; + main_maccore_maccore_bus_errors_re <= 1'd0; + main_maccore_maccore_bus_errors <= 32'd0; + main_maccore_ethphy_reset_storage <= 1'd0; + main_maccore_ethphy_reset_re <= 1'd0; + main_maccore_ethphy_re <= 1'd0; + main_maccore_ethphy__w_storage <= 3'd0; + main_maccore_ethphy__w_re <= 1'd0; + main_maccore_ethphy__r_re <= 1'd0; + main_re <= 1'd0; + main_tx_cdc_cdc_graycounter0_q <= 6'd0; + main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; + main_preamble_errors_status <= 32'd0; + main_preamble_errors_re <= 1'd0; + main_crc_errors_status <= 32'd0; + main_crc_errors_re <= 1'd0; + main_rx_cdc_cdc_graycounter1_q <= 6'd0; + main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_sram9_re <= 1'd0; + main_sram12_re <= 1'd0; + main_sram13_status <= 32'd0; + main_sram15_re <= 1'd0; + main_sram24_re <= 1'd0; + main_sram28_re <= 1'd0; + main_sram29_r <= 1'd0; + main_sram31_storage <= 1'd0; + main_sram32_re <= 1'd0; + main_slot <= 1'd0; + main_sram35_length <= 11'd0; + main_sram55_level <= 2'd0; + main_sram57_produce <= 1'd0; + main_sram58_consume <= 1'd0; + main_sram96_re <= 1'd0; + main_sram99_re <= 1'd0; + main_sram101_re <= 1'd0; + main_sram103_re <= 1'd0; + main_sram106_pending <= 1'd0; + main_sram112_re <= 1'd0; + main_sram116_re <= 1'd0; + main_sram117_r <= 1'd0; + main_sram119_storage <= 1'd0; + main_sram120_re <= 1'd0; + main_sram122_length <= 11'd0; + main_sram141_level <= 2'd0; + main_sram143_produce <= 1'd0; + main_sram144_consume <= 1'd0; + main_interface0_ack <= 1'd0; + main_interface1_ack <= 1'd0; + main_interface2_ack <= 1'd0; + main_interface3_ack <= 1'd0; + main_slave_sel_r <= 4'd0; + builder_slave_sel_r <= 2'd0; + builder_count <= 20'd1000000; + builder_maccore_liteethmacsramwriter_state <= 2'd0; + builder_maccore_liteethmacsramreader_state <= 2'd0; + builder_maccore_state <= 1'd0; + end + builder_multiregimpl0_regs0 <= main_maccore_ethphy_data_r; + builder_multiregimpl0_regs1 <= builder_multiregimpl0_regs0; + builder_multiregimpl2_regs0 <= main_tx_cdc_cdc_graycounter1_q; + builder_multiregimpl2_regs1 <= builder_multiregimpl2_regs0; + builder_multiregimpl3_regs0 <= main_pulsesynchronizer0_toggle_i; + builder_multiregimpl3_regs1 <= builder_multiregimpl3_regs0; + builder_multiregimpl4_regs0 <= main_pulsesynchronizer1_toggle_i; + builder_multiregimpl4_regs1 <= builder_multiregimpl4_regs0; + builder_multiregimpl5_regs0 <= main_rx_cdc_cdc_graycounter0_q; + builder_multiregimpl5_regs1 <= builder_multiregimpl5_regs0; +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +DELAYG #( + .DEL_MODE("SCLK_ALIGNED"), + .DEL_VALUE(7'd80) +) DELAYG ( + .A(main_maccore_ethphy_eth_tx_clk_o), + .Z(rgmii_eth_clocks_tx) +); + +DELAYG #( + .DEL_MODE("SCLK_ALIGNED"), + .DEL_VALUE(1'd0) +) DELAYG_1 ( + .A(main_maccore_ethphy_tx_ctl_oddrx1f), + .Z(rgmii_eth_tx_ctl) +); + +DELAYG #( + .DEL_MODE("SCLK_ALIGNED"), + .DEL_VALUE(1'd0) +) DELAYG_2 ( + .A(main_maccore_ethphy_tx_data_oddrx1f[0]), + .Z(rgmii_eth_tx_data[0]) +); + +DELAYG #( + .DEL_MODE("SCLK_ALIGNED"), + .DEL_VALUE(1'd0) +) DELAYG_3 ( + .A(main_maccore_ethphy_tx_data_oddrx1f[1]), + .Z(rgmii_eth_tx_data[1]) +); + +DELAYG #( + .DEL_MODE("SCLK_ALIGNED"), + .DEL_VALUE(1'd0) +) DELAYG_4 ( + .A(main_maccore_ethphy_tx_data_oddrx1f[2]), + .Z(rgmii_eth_tx_data[2]) +); + +DELAYG #( + .DEL_MODE("SCLK_ALIGNED"), + .DEL_VALUE(1'd0) +) DELAYG_5 ( + .A(main_maccore_ethphy_tx_data_oddrx1f[3]), + .Z(rgmii_eth_tx_data[3]) +); + +DELAYG #( + .DEL_MODE("SCLK_ALIGNED"), + .DEL_VALUE(7'd80) +) DELAYG_6 ( + .A(rgmii_eth_rx_ctl), + .Z(main_maccore_ethphy_rx_ctl_delayf) +); + +DELAYG #( + .DEL_MODE("SCLK_ALIGNED"), + .DEL_VALUE(7'd80) +) DELAYG_7 ( + .A(rgmii_eth_rx_data[0]), + .Z(main_maccore_ethphy_rx_data_delayf[0]) +); + +DELAYG #( + .DEL_MODE("SCLK_ALIGNED"), + .DEL_VALUE(7'd80) +) DELAYG_8 ( + .A(rgmii_eth_rx_data[1]), + .Z(main_maccore_ethphy_rx_data_delayf[1]) +); + +DELAYG #( + .DEL_MODE("SCLK_ALIGNED"), + .DEL_VALUE(7'd80) +) DELAYG_9 ( + .A(rgmii_eth_rx_data[2]), + .Z(main_maccore_ethphy_rx_data_delayf[2]) +); + +DELAYG #( + .DEL_MODE("SCLK_ALIGNED"), + .DEL_VALUE(7'd80) +) DELAYG_10 ( + .A(rgmii_eth_rx_data[3]), + .Z(main_maccore_ethphy_rx_data_delayf[3]) +); + +//------------------------------------------------------------------------------ +// Memory storage: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | +reg [41:0] storage[0:31]; +reg [41:0] storage_dat0; +reg [41:0] storage_dat1; +always @(posedge sys_clk) begin + if (main_tx_cdc_cdc_wrport_we) + storage[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; + storage_dat0 <= storage[main_tx_cdc_cdc_wrport_adr]; +end +always @(posedge eth_tx_clk) begin + storage_dat1 <= storage[main_tx_cdc_cdc_rdport_adr]; +end +assign main_tx_cdc_cdc_wrport_dat_r = storage_dat0; +assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 5-words x 12-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 12 +// Port 1 | Read: Async | Write: ---- | +reg [11:0] storage_1[0:4]; +reg [11:0] storage_1_dat0; +always @(posedge eth_rx_clk) begin + if (main_rx_crc_syncfifo_wrport_we) + storage_1[main_rx_crc_syncfifo_wrport_adr] <= main_rx_crc_syncfifo_wrport_dat_w; + storage_1_dat0 <= storage_1[main_rx_crc_syncfifo_wrport_adr]; +end +always @(posedge eth_rx_clk) begin +end +assign main_rx_crc_syncfifo_wrport_dat_r = storage_1_dat0; +assign main_rx_crc_syncfifo_rdport_dat_r = storage_1[main_rx_crc_syncfifo_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_2: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | +reg [41:0] storage_2[0:31]; +reg [41:0] storage_2_dat0; +reg [41:0] storage_2_dat1; +always @(posedge eth_rx_clk) begin + if (main_rx_cdc_cdc_wrport_we) + storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w; + storage_2_dat0 <= storage_2[main_rx_cdc_cdc_wrport_adr]; +end +always @(posedge sys_clk) begin + storage_2_dat1 <= storage_2[main_rx_cdc_cdc_rdport_adr]; +end +assign main_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; +assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_3: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | +reg [13:0] storage_3[0:1]; +reg [13:0] storage_3_dat0; +always @(posedge sys_clk) begin + if (main_sram61_we) + storage_3[main_sram59_adr] <= main_sram62_dat_w; + storage_3_dat0 <= storage_3[main_sram59_adr]; +end +always @(posedge sys_clk) begin +end +assign main_sram60_dat_r = storage_3_dat0; +assign main_sram65_dat_r = storage_3[main_sram64_adr]; + + +//------------------------------------------------------------------------------ +// Memory mem: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem[0:382]; +reg [8:0] mem_adr0; +reg [31:0] mem_dat1; +always @(posedge sys_clk) begin + if (main_sram77_we) + mem[main_sram75_adr] <= main_sram78_dat_w; + mem_adr0 <= main_sram75_adr; +end +always @(posedge sys_clk) begin + mem_dat1 <= mem[main_sram0_adr]; +end +assign main_sram76_dat_r = mem[mem_adr0]; +assign main_sram0_dat_r = mem_dat1; + + +//------------------------------------------------------------------------------ +// Memory mem_1: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem_1[0:382]; +reg [8:0] mem_1_adr0; +reg [31:0] mem_1_dat1; +always @(posedge sys_clk) begin + if (main_sram81_we) + mem_1[main_sram79_adr] <= main_sram82_dat_w; + mem_1_adr0 <= main_sram79_adr; +end +always @(posedge sys_clk) begin + mem_1_dat1 <= mem_1[main_sram1_adr]; +end +assign main_sram80_dat_r = mem_1[mem_1_adr0]; +assign main_sram1_dat_r = mem_1_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_4: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | +reg [13:0] storage_4[0:1]; +reg [13:0] storage_4_dat0; +always @(posedge sys_clk) begin + if (main_sram147_we) + storage_4[main_sram145_adr] <= main_sram148_dat_w; + storage_4_dat0 <= storage_4[main_sram145_adr]; +end +always @(posedge sys_clk) begin +end +assign main_sram146_dat_r = storage_4_dat0; +assign main_sram151_dat_r = storage_4[main_sram150_adr]; + + +//------------------------------------------------------------------------------ +// Memory mem_2: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_2[0:382]; +reg [8:0] mem_2_adr0; +reg [8:0] mem_2_adr1; +always @(posedge sys_clk) begin + if (main_sram163_re) + mem_2_adr0 <= main_sram161_adr; +end +always @(posedge sys_clk) begin + if (main_sram2_we[0]) + mem_2[main_sram2_adr][7:0] <= main_sram2_dat_w[7:0]; + if (main_sram2_we[1]) + mem_2[main_sram2_adr][15:8] <= main_sram2_dat_w[15:8]; + if (main_sram2_we[2]) + mem_2[main_sram2_adr][23:16] <= main_sram2_dat_w[23:16]; + if (main_sram2_we[3]) + mem_2[main_sram2_adr][31:24] <= main_sram2_dat_w[31:24]; + mem_2_adr1 <= main_sram2_adr; +end +assign main_sram162_dat_r = mem_2[mem_2_adr0]; +assign main_sram2_dat_r = mem_2[mem_2_adr1]; + + +//------------------------------------------------------------------------------ +// Memory mem_3: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_3[0:382]; +reg [8:0] mem_3_adr0; +reg [8:0] mem_3_adr1; +always @(posedge sys_clk) begin + if (main_sram166_re) + mem_3_adr0 <= main_sram164_adr; +end +always @(posedge sys_clk) begin + if (main_sram3_we[0]) + mem_3[main_sram3_adr][7:0] <= main_sram3_dat_w[7:0]; + if (main_sram3_we[1]) + mem_3[main_sram3_adr][15:8] <= main_sram3_dat_w[15:8]; + if (main_sram3_we[2]) + mem_3[main_sram3_adr][23:16] <= main_sram3_dat_w[23:16]; + if (main_sram3_we[3]) + mem_3[main_sram3_adr][31:24] <= main_sram3_dat_w[31:24]; + mem_3_adr1 <= main_sram3_adr; +end +assign main_sram165_dat_r = mem_3[mem_3_adr0]; +assign main_sram3_dat_r = mem_3[mem_3_adr1]; + + +ODDRX1F ODDRX1F( + .D0(1'd1), + .D1(1'd0), + .SCLK(eth_tx_clk), + .Q(main_maccore_ethphy_eth_tx_clk_o) +); + +FD1S3BX FD1S3BX( + .CK(eth_tx_clk), + .D(1'd0), + .PD(main_maccore_ethphy_reset), + .Q(builder_rst10) +); + +FD1S3BX FD1S3BX_1( + .CK(eth_tx_clk), + .D(builder_rst10), + .PD(main_maccore_ethphy_reset), + .Q(eth_tx_rst) +); + +FD1S3BX FD1S3BX_2( + .CK(eth_rx_clk), + .D(1'd0), + .PD(main_maccore_ethphy_reset), + .Q(builder_rst11) +); + +FD1S3BX FD1S3BX_3( + .CK(eth_rx_clk), + .D(builder_rst11), + .PD(main_maccore_ethphy_reset), + .Q(eth_rx_rst) +); + +ODDRX1F ODDRX1F_1( + .D0(main_maccore_ethphy_sink_valid), + .D1(main_maccore_ethphy_sink_valid), + .SCLK(eth_tx_clk), + .Q(main_maccore_ethphy_tx_ctl_oddrx1f) +); + +ODDRX1F ODDRX1F_2( + .D0(main_maccore_ethphy_sink_payload_data[0]), + .D1(main_maccore_ethphy_sink_payload_data[4]), + .SCLK(eth_tx_clk), + .Q(main_maccore_ethphy_tx_data_oddrx1f[0]) +); + +ODDRX1F ODDRX1F_3( + .D0(main_maccore_ethphy_sink_payload_data[1]), + .D1(main_maccore_ethphy_sink_payload_data[5]), + .SCLK(eth_tx_clk), + .Q(main_maccore_ethphy_tx_data_oddrx1f[1]) +); + +ODDRX1F ODDRX1F_4( + .D0(main_maccore_ethphy_sink_payload_data[2]), + .D1(main_maccore_ethphy_sink_payload_data[6]), + .SCLK(eth_tx_clk), + .Q(main_maccore_ethphy_tx_data_oddrx1f[2]) +); + +ODDRX1F ODDRX1F_5( + .D0(main_maccore_ethphy_sink_payload_data[3]), + .D1(main_maccore_ethphy_sink_payload_data[7]), + .SCLK(eth_tx_clk), + .Q(main_maccore_ethphy_tx_data_oddrx1f[3]) +); + +IDDRX1F IDDRX1F( + .D(main_maccore_ethphy_rx_ctl_delayf), + .SCLK(eth_rx_clk), + .Q0(main_maccore_ethphy_rx_ctl[0]), + .Q1(main_maccore_ethphy_rx_ctl[1]) +); + +IDDRX1F IDDRX1F_1( + .D(main_maccore_ethphy_rx_data_delayf[0]), + .SCLK(eth_rx_clk), + .Q0(main_maccore_ethphy_rx_data[0]), + .Q1(main_maccore_ethphy_rx_data[4]) +); + +IDDRX1F IDDRX1F_2( + .D(main_maccore_ethphy_rx_data_delayf[1]), + .SCLK(eth_rx_clk), + .Q0(main_maccore_ethphy_rx_data[1]), + .Q1(main_maccore_ethphy_rx_data[5]) +); + +IDDRX1F IDDRX1F_3( + .D(main_maccore_ethphy_rx_data_delayf[2]), + .SCLK(eth_rx_clk), + .Q0(main_maccore_ethphy_rx_data[2]), + .Q1(main_maccore_ethphy_rx_data[6]) +); + +IDDRX1F IDDRX1F_4( + .D(main_maccore_ethphy_rx_data_delayf[3]), + .SCLK(eth_rx_clk), + .Q0(main_maccore_ethphy_rx_data[3]), + .Q1(main_maccore_ethphy_rx_data[7]) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO ( + .B(rgmii_eth_mdio), + .I(main_maccore_ethphy_data_w), + .T((~main_maccore_ethphy_data_oe)), + .O(main_maccore_ethphy_data_r) +); + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2023-02-07 21:33:18. +//------------------------------------------------------------------------------ diff --git a/gateware/liteeth/gateware/liteeth_core.ys b/gateware/liteeth/gateware/liteeth_core.ys new file mode 100644 index 0000000..bd2033a --- /dev/null +++ b/gateware/liteeth/gateware/liteeth_core.ys @@ -0,0 +1,8 @@ +verilog_defaults -push +verilog_defaults -add -defer +read_verilog /home/david/ARVP/sonar_fpga/gateware/liteeth/gateware/liteeth_core.v +verilog_defaults -pop +attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0 + +synth_ecp5 -top liteeth_core +write_json liteeth_core.json \ No newline at end of file diff --git a/gateware/liteeth/software/include/generated/csr.h b/gateware/liteeth/software/include/generated/csr.h new file mode 100644 index 0000000..81afd86 --- /dev/null +++ b/gateware/liteeth/software/include/generated/csr.h @@ -0,0 +1,409 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by LiteX (8159b5ca) on 2023-02-07 21:33:18 +//-------------------------------------------------------------------------------- +#include +#ifndef __GENERATED_CSR_H +#define __GENERATED_CSR_H +#include +#include +#ifndef CSR_ACCESSORS_DEFINED +#include +#endif /* ! CSR_ACCESSORS_DEFINED */ +#ifndef CSR_BASE +#define CSR_BASE 0x0L +#endif + +/* ctrl */ +#define CSR_CTRL_BASE (CSR_BASE + 0x0L) +#define CSR_CTRL_RESET_ADDR (CSR_BASE + 0x0L) +#define CSR_CTRL_RESET_SIZE 1 +static inline uint32_t ctrl_reset_read(void) { + return csr_read_simple((CSR_BASE + 0x0L)); +} +static inline void ctrl_reset_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x0L)); +} +#define CSR_CTRL_RESET_SOC_RST_OFFSET 0 +#define CSR_CTRL_RESET_SOC_RST_SIZE 1 +static inline uint32_t ctrl_reset_soc_rst_extract(uint32_t oldword) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return ( (oldword >> 0) & mask ); +} +static inline uint32_t ctrl_reset_soc_rst_read(void) { + uint32_t word = ctrl_reset_read(); + return ctrl_reset_soc_rst_extract(word); +} +static inline uint32_t ctrl_reset_soc_rst_replace(uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ; +} +static inline void ctrl_reset_soc_rst_write(uint32_t plain_value) { + uint32_t oldword = ctrl_reset_read(); + uint32_t newword = ctrl_reset_soc_rst_replace(oldword, plain_value); + ctrl_reset_write(newword); +} +#define CSR_CTRL_RESET_CPU_RST_OFFSET 1 +#define CSR_CTRL_RESET_CPU_RST_SIZE 1 +static inline uint32_t ctrl_reset_cpu_rst_extract(uint32_t oldword) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return ( (oldword >> 1) & mask ); +} +static inline uint32_t ctrl_reset_cpu_rst_read(void) { + uint32_t word = ctrl_reset_read(); + return ctrl_reset_cpu_rst_extract(word); +} +static inline uint32_t ctrl_reset_cpu_rst_replace(uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ; +} +static inline void ctrl_reset_cpu_rst_write(uint32_t plain_value) { + uint32_t oldword = ctrl_reset_read(); + uint32_t newword = ctrl_reset_cpu_rst_replace(oldword, plain_value); + ctrl_reset_write(newword); +} +#define CSR_CTRL_SCRATCH_ADDR (CSR_BASE + 0x4L) +#define CSR_CTRL_SCRATCH_SIZE 1 +static inline uint32_t ctrl_scratch_read(void) { + return csr_read_simple((CSR_BASE + 0x4L)); +} +static inline void ctrl_scratch_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x4L)); +} +#define CSR_CTRL_BUS_ERRORS_ADDR (CSR_BASE + 0x8L) +#define CSR_CTRL_BUS_ERRORS_SIZE 1 +static inline uint32_t ctrl_bus_errors_read(void) { + return csr_read_simple((CSR_BASE + 0x8L)); +} + +/* ethmac */ +#define CSR_ETHMAC_BASE (CSR_BASE + 0x800L) +#define CSR_ETHMAC_SRAM_WRITER_SLOT_ADDR (CSR_BASE + 0x800L) +#define CSR_ETHMAC_SRAM_WRITER_SLOT_SIZE 1 +static inline uint32_t ethmac_sram_writer_slot_read(void) { + return csr_read_simple((CSR_BASE + 0x800L)); +} +#define CSR_ETHMAC_SRAM_WRITER_LENGTH_ADDR (CSR_BASE + 0x804L) +#define CSR_ETHMAC_SRAM_WRITER_LENGTH_SIZE 1 +static inline uint32_t ethmac_sram_writer_length_read(void) { + return csr_read_simple((CSR_BASE + 0x804L)); +} +#define CSR_ETHMAC_SRAM_WRITER_ERRORS_ADDR (CSR_BASE + 0x808L) +#define CSR_ETHMAC_SRAM_WRITER_ERRORS_SIZE 1 +static inline uint32_t ethmac_sram_writer_errors_read(void) { + return csr_read_simple((CSR_BASE + 0x808L)); +} +#define CSR_ETHMAC_SRAM_WRITER_EV_STATUS_ADDR (CSR_BASE + 0x80cL) +#define CSR_ETHMAC_SRAM_WRITER_EV_STATUS_SIZE 1 +static inline uint32_t ethmac_sram_writer_ev_status_read(void) { + return csr_read_simple((CSR_BASE + 0x80cL)); +} +#define CSR_ETHMAC_SRAM_WRITER_EV_STATUS_AVAILABLE_OFFSET 0 +#define CSR_ETHMAC_SRAM_WRITER_EV_STATUS_AVAILABLE_SIZE 1 +static inline uint32_t ethmac_sram_writer_ev_status_available_extract(uint32_t oldword) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return ( (oldword >> 0) & mask ); +} +static inline uint32_t ethmac_sram_writer_ev_status_available_read(void) { + uint32_t word = ethmac_sram_writer_ev_status_read(); + return ethmac_sram_writer_ev_status_available_extract(word); +} +#define CSR_ETHMAC_SRAM_WRITER_EV_PENDING_ADDR (CSR_BASE + 0x810L) +#define CSR_ETHMAC_SRAM_WRITER_EV_PENDING_SIZE 1 +static inline uint32_t ethmac_sram_writer_ev_pending_read(void) { + return csr_read_simple((CSR_BASE + 0x810L)); +} +static inline void ethmac_sram_writer_ev_pending_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x810L)); +} +#define CSR_ETHMAC_SRAM_WRITER_EV_PENDING_AVAILABLE_OFFSET 0 +#define CSR_ETHMAC_SRAM_WRITER_EV_PENDING_AVAILABLE_SIZE 1 +static inline uint32_t ethmac_sram_writer_ev_pending_available_extract(uint32_t oldword) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return ( (oldword >> 0) & mask ); +} +static inline uint32_t ethmac_sram_writer_ev_pending_available_read(void) { + uint32_t word = ethmac_sram_writer_ev_pending_read(); + return ethmac_sram_writer_ev_pending_available_extract(word); +} +static inline uint32_t ethmac_sram_writer_ev_pending_available_replace(uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ; +} +static inline void ethmac_sram_writer_ev_pending_available_write(uint32_t plain_value) { + uint32_t oldword = ethmac_sram_writer_ev_pending_read(); + uint32_t newword = ethmac_sram_writer_ev_pending_available_replace(oldword, plain_value); + ethmac_sram_writer_ev_pending_write(newword); +} +#define CSR_ETHMAC_SRAM_WRITER_EV_ENABLE_ADDR (CSR_BASE + 0x814L) +#define CSR_ETHMAC_SRAM_WRITER_EV_ENABLE_SIZE 1 +static inline uint32_t ethmac_sram_writer_ev_enable_read(void) { + return csr_read_simple((CSR_BASE + 0x814L)); +} +static inline void ethmac_sram_writer_ev_enable_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x814L)); +} +#define CSR_ETHMAC_SRAM_WRITER_EV_ENABLE_AVAILABLE_OFFSET 0 +#define CSR_ETHMAC_SRAM_WRITER_EV_ENABLE_AVAILABLE_SIZE 1 +static inline uint32_t ethmac_sram_writer_ev_enable_available_extract(uint32_t oldword) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return ( (oldword >> 0) & mask ); +} +static inline uint32_t ethmac_sram_writer_ev_enable_available_read(void) { + uint32_t word = ethmac_sram_writer_ev_enable_read(); + return ethmac_sram_writer_ev_enable_available_extract(word); +} +static inline uint32_t ethmac_sram_writer_ev_enable_available_replace(uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ; +} +static inline void ethmac_sram_writer_ev_enable_available_write(uint32_t plain_value) { + uint32_t oldword = ethmac_sram_writer_ev_enable_read(); + uint32_t newword = ethmac_sram_writer_ev_enable_available_replace(oldword, plain_value); + ethmac_sram_writer_ev_enable_write(newword); +} +#define CSR_ETHMAC_SRAM_READER_START_ADDR (CSR_BASE + 0x818L) +#define CSR_ETHMAC_SRAM_READER_START_SIZE 1 +static inline uint32_t ethmac_sram_reader_start_read(void) { + return csr_read_simple((CSR_BASE + 0x818L)); +} +static inline void ethmac_sram_reader_start_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x818L)); +} +#define CSR_ETHMAC_SRAM_READER_READY_ADDR (CSR_BASE + 0x81cL) +#define CSR_ETHMAC_SRAM_READER_READY_SIZE 1 +static inline uint32_t ethmac_sram_reader_ready_read(void) { + return csr_read_simple((CSR_BASE + 0x81cL)); +} +#define CSR_ETHMAC_SRAM_READER_LEVEL_ADDR (CSR_BASE + 0x820L) +#define CSR_ETHMAC_SRAM_READER_LEVEL_SIZE 1 +static inline uint32_t ethmac_sram_reader_level_read(void) { + return csr_read_simple((CSR_BASE + 0x820L)); +} +#define CSR_ETHMAC_SRAM_READER_SLOT_ADDR (CSR_BASE + 0x824L) +#define CSR_ETHMAC_SRAM_READER_SLOT_SIZE 1 +static inline uint32_t ethmac_sram_reader_slot_read(void) { + return csr_read_simple((CSR_BASE + 0x824L)); +} +static inline void ethmac_sram_reader_slot_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x824L)); +} +#define CSR_ETHMAC_SRAM_READER_LENGTH_ADDR (CSR_BASE + 0x828L) +#define CSR_ETHMAC_SRAM_READER_LENGTH_SIZE 1 +static inline uint32_t ethmac_sram_reader_length_read(void) { + return csr_read_simple((CSR_BASE + 0x828L)); +} +static inline void ethmac_sram_reader_length_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x828L)); +} +#define CSR_ETHMAC_SRAM_READER_EV_STATUS_ADDR (CSR_BASE + 0x82cL) +#define CSR_ETHMAC_SRAM_READER_EV_STATUS_SIZE 1 +static inline uint32_t ethmac_sram_reader_ev_status_read(void) { + return csr_read_simple((CSR_BASE + 0x82cL)); +} +#define CSR_ETHMAC_SRAM_READER_EV_STATUS_EVENT0_OFFSET 0 +#define CSR_ETHMAC_SRAM_READER_EV_STATUS_EVENT0_SIZE 1 +static inline uint32_t ethmac_sram_reader_ev_status_event0_extract(uint32_t oldword) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return ( (oldword >> 0) & mask ); +} +static inline uint32_t ethmac_sram_reader_ev_status_event0_read(void) { + uint32_t word = ethmac_sram_reader_ev_status_read(); + return ethmac_sram_reader_ev_status_event0_extract(word); +} +#define CSR_ETHMAC_SRAM_READER_EV_PENDING_ADDR (CSR_BASE + 0x830L) +#define CSR_ETHMAC_SRAM_READER_EV_PENDING_SIZE 1 +static inline uint32_t ethmac_sram_reader_ev_pending_read(void) { + return csr_read_simple((CSR_BASE + 0x830L)); +} +static inline void ethmac_sram_reader_ev_pending_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x830L)); +} +#define CSR_ETHMAC_SRAM_READER_EV_PENDING_EVENT0_OFFSET 0 +#define CSR_ETHMAC_SRAM_READER_EV_PENDING_EVENT0_SIZE 1 +static inline uint32_t ethmac_sram_reader_ev_pending_event0_extract(uint32_t oldword) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return ( (oldword >> 0) & mask ); +} +static inline uint32_t ethmac_sram_reader_ev_pending_event0_read(void) { + uint32_t word = ethmac_sram_reader_ev_pending_read(); + return ethmac_sram_reader_ev_pending_event0_extract(word); +} +static inline uint32_t ethmac_sram_reader_ev_pending_event0_replace(uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ; +} +static inline void ethmac_sram_reader_ev_pending_event0_write(uint32_t plain_value) { + uint32_t oldword = ethmac_sram_reader_ev_pending_read(); + uint32_t newword = ethmac_sram_reader_ev_pending_event0_replace(oldword, plain_value); + ethmac_sram_reader_ev_pending_write(newword); +} +#define CSR_ETHMAC_SRAM_READER_EV_ENABLE_ADDR (CSR_BASE + 0x834L) +#define CSR_ETHMAC_SRAM_READER_EV_ENABLE_SIZE 1 +static inline uint32_t ethmac_sram_reader_ev_enable_read(void) { + return csr_read_simple((CSR_BASE + 0x834L)); +} +static inline void ethmac_sram_reader_ev_enable_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x834L)); +} +#define CSR_ETHMAC_SRAM_READER_EV_ENABLE_EVENT0_OFFSET 0 +#define CSR_ETHMAC_SRAM_READER_EV_ENABLE_EVENT0_SIZE 1 +static inline uint32_t ethmac_sram_reader_ev_enable_event0_extract(uint32_t oldword) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return ( (oldword >> 0) & mask ); +} +static inline uint32_t ethmac_sram_reader_ev_enable_event0_read(void) { + uint32_t word = ethmac_sram_reader_ev_enable_read(); + return ethmac_sram_reader_ev_enable_event0_extract(word); +} +static inline uint32_t ethmac_sram_reader_ev_enable_event0_replace(uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ; +} +static inline void ethmac_sram_reader_ev_enable_event0_write(uint32_t plain_value) { + uint32_t oldword = ethmac_sram_reader_ev_enable_read(); + uint32_t newword = ethmac_sram_reader_ev_enable_event0_replace(oldword, plain_value); + ethmac_sram_reader_ev_enable_write(newword); +} +#define CSR_ETHMAC_PREAMBLE_CRC_ADDR (CSR_BASE + 0x838L) +#define CSR_ETHMAC_PREAMBLE_CRC_SIZE 1 +static inline uint32_t ethmac_preamble_crc_read(void) { + return csr_read_simple((CSR_BASE + 0x838L)); +} +#define CSR_ETHMAC_RX_DATAPATH_PREAMBLE_ERRORS_ADDR (CSR_BASE + 0x83cL) +#define CSR_ETHMAC_RX_DATAPATH_PREAMBLE_ERRORS_SIZE 1 +static inline uint32_t ethmac_rx_datapath_preamble_errors_read(void) { + return csr_read_simple((CSR_BASE + 0x83cL)); +} +#define CSR_ETHMAC_RX_DATAPATH_CRC_ERRORS_ADDR (CSR_BASE + 0x840L) +#define CSR_ETHMAC_RX_DATAPATH_CRC_ERRORS_SIZE 1 +static inline uint32_t ethmac_rx_datapath_crc_errors_read(void) { + return csr_read_simple((CSR_BASE + 0x840L)); +} + +/* ethphy */ +#define CSR_ETHPHY_BASE (CSR_BASE + 0x1000L) +#define CSR_ETHPHY_CRG_RESET_ADDR (CSR_BASE + 0x1000L) +#define CSR_ETHPHY_CRG_RESET_SIZE 1 +static inline uint32_t ethphy_crg_reset_read(void) { + return csr_read_simple((CSR_BASE + 0x1000L)); +} +static inline void ethphy_crg_reset_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x1000L)); +} +#define CSR_ETHPHY_RX_INBAND_STATUS_ADDR (CSR_BASE + 0x1004L) +#define CSR_ETHPHY_RX_INBAND_STATUS_SIZE 1 +static inline uint32_t ethphy_rx_inband_status_read(void) { + return csr_read_simple((CSR_BASE + 0x1004L)); +} +#define CSR_ETHPHY_RX_INBAND_STATUS_LINK_STATUS_OFFSET 0 +#define CSR_ETHPHY_RX_INBAND_STATUS_LINK_STATUS_SIZE 1 +static inline uint32_t ethphy_rx_inband_status_link_status_extract(uint32_t oldword) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return ( (oldword >> 0) & mask ); +} +static inline uint32_t ethphy_rx_inband_status_link_status_read(void) { + uint32_t word = ethphy_rx_inband_status_read(); + return ethphy_rx_inband_status_link_status_extract(word); +} +#define CSR_ETHPHY_RX_INBAND_STATUS_CLOCK_SPEED_OFFSET 1 +#define CSR_ETHPHY_RX_INBAND_STATUS_CLOCK_SPEED_SIZE 1 +static inline uint32_t ethphy_rx_inband_status_clock_speed_extract(uint32_t oldword) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return ( (oldword >> 1) & mask ); +} +static inline uint32_t ethphy_rx_inband_status_clock_speed_read(void) { + uint32_t word = ethphy_rx_inband_status_read(); + return ethphy_rx_inband_status_clock_speed_extract(word); +} +#define CSR_ETHPHY_RX_INBAND_STATUS_DUPLEX_STATUS_OFFSET 2 +#define CSR_ETHPHY_RX_INBAND_STATUS_DUPLEX_STATUS_SIZE 1 +static inline uint32_t ethphy_rx_inband_status_duplex_status_extract(uint32_t oldword) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return ( (oldword >> 2) & mask ); +} +static inline uint32_t ethphy_rx_inband_status_duplex_status_read(void) { + uint32_t word = ethphy_rx_inband_status_read(); + return ethphy_rx_inband_status_duplex_status_extract(word); +} +#define CSR_ETHPHY_MDIO_W_ADDR (CSR_BASE + 0x1008L) +#define CSR_ETHPHY_MDIO_W_SIZE 1 +static inline uint32_t ethphy_mdio_w_read(void) { + return csr_read_simple((CSR_BASE + 0x1008L)); +} +static inline void ethphy_mdio_w_write(uint32_t v) { + csr_write_simple(v, (CSR_BASE + 0x1008L)); +} +#define CSR_ETHPHY_MDIO_W_MDC_OFFSET 0 +#define CSR_ETHPHY_MDIO_W_MDC_SIZE 1 +static inline uint32_t ethphy_mdio_w_mdc_extract(uint32_t oldword) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return ( (oldword >> 0) & mask ); +} +static inline uint32_t ethphy_mdio_w_mdc_read(void) { + uint32_t word = ethphy_mdio_w_read(); + return ethphy_mdio_w_mdc_extract(word); +} +static inline uint32_t ethphy_mdio_w_mdc_replace(uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ; +} +static inline void ethphy_mdio_w_mdc_write(uint32_t plain_value) { + uint32_t oldword = ethphy_mdio_w_read(); + uint32_t newword = ethphy_mdio_w_mdc_replace(oldword, plain_value); + ethphy_mdio_w_write(newword); +} +#define CSR_ETHPHY_MDIO_W_OE_OFFSET 1 +#define CSR_ETHPHY_MDIO_W_OE_SIZE 1 +static inline uint32_t ethphy_mdio_w_oe_extract(uint32_t oldword) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return ( (oldword >> 1) & mask ); +} +static inline uint32_t ethphy_mdio_w_oe_read(void) { + uint32_t word = ethphy_mdio_w_read(); + return ethphy_mdio_w_oe_extract(word); +} +static inline uint32_t ethphy_mdio_w_oe_replace(uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ; +} +static inline void ethphy_mdio_w_oe_write(uint32_t plain_value) { + uint32_t oldword = ethphy_mdio_w_read(); + uint32_t newword = ethphy_mdio_w_oe_replace(oldword, plain_value); + ethphy_mdio_w_write(newword); +} +#define CSR_ETHPHY_MDIO_W_W_OFFSET 2 +#define CSR_ETHPHY_MDIO_W_W_SIZE 1 +static inline uint32_t ethphy_mdio_w_w_extract(uint32_t oldword) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return ( (oldword >> 2) & mask ); +} +static inline uint32_t ethphy_mdio_w_w_read(void) { + uint32_t word = ethphy_mdio_w_read(); + return ethphy_mdio_w_w_extract(word); +} +static inline uint32_t ethphy_mdio_w_w_replace(uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return (oldword & (~(mask << 2))) | (mask & plain_value)<< 2 ; +} +static inline void ethphy_mdio_w_w_write(uint32_t plain_value) { + uint32_t oldword = ethphy_mdio_w_read(); + uint32_t newword = ethphy_mdio_w_w_replace(oldword, plain_value); + ethphy_mdio_w_write(newword); +} +#define CSR_ETHPHY_MDIO_R_ADDR (CSR_BASE + 0x100cL) +#define CSR_ETHPHY_MDIO_R_SIZE 1 +static inline uint32_t ethphy_mdio_r_read(void) { + return csr_read_simple((CSR_BASE + 0x100cL)); +} +#define CSR_ETHPHY_MDIO_R_R_OFFSET 0 +#define CSR_ETHPHY_MDIO_R_R_SIZE 1 +static inline uint32_t ethphy_mdio_r_r_extract(uint32_t oldword) { + uint32_t mask = ((uint32_t)(1 << 1)-1); + return ( (oldword >> 0) & mask ); +} +static inline uint32_t ethphy_mdio_r_r_read(void) { + uint32_t word = ethphy_mdio_r_read(); + return ethphy_mdio_r_r_extract(word); +} + +#endif diff --git a/gateware/liteeth/software/include/generated/git.h b/gateware/liteeth/software/include/generated/git.h new file mode 100644 index 0000000..7e521a3 --- /dev/null +++ b/gateware/liteeth/software/include/generated/git.h @@ -0,0 +1,8 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by LiteX (8159b5ca) on 2023-02-07 21:33:18 +//-------------------------------------------------------------------------------- +#ifndef __GENERATED_GIT_H +#define __GENERATED_GIT_H + +#define LITEX_GIT_SHA1 "8159b5ca" +#endif diff --git a/gateware/liteeth/software/include/generated/mem.h b/gateware/liteeth/software/include/generated/mem.h new file mode 100644 index 0000000..5996c5e --- /dev/null +++ b/gateware/liteeth/software/include/generated/mem.h @@ -0,0 +1,20 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by LiteX (8159b5ca) on 2023-02-07 21:33:18 +//-------------------------------------------------------------------------------- +#ifndef __GENERATED_MEM_H +#define __GENERATED_MEM_H + +#ifndef ETHMAC_BASE +#define ETHMAC_BASE 0x00020000L +#define ETHMAC_SIZE 0x00002000 +#endif + +#ifndef CSR_BASE +#define CSR_BASE 0x00000000L +#define CSR_SIZE 0x00010000 +#endif + +#ifndef MEM_REGIONS +#define MEM_REGIONS "ETHMAC 0x00020000 0x2000 \nCSR 0x00000000 0x10000 " +#endif +#endif diff --git a/gateware/liteeth/software/include/generated/soc.h b/gateware/liteeth/software/include/generated/soc.h new file mode 100644 index 0000000..b2f186a --- /dev/null +++ b/gateware/liteeth/software/include/generated/soc.h @@ -0,0 +1,56 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by LiteX (8159b5ca) on 2023-02-07 21:33:18 +//-------------------------------------------------------------------------------- +#ifndef __GENERATED_SOC_H +#define __GENERATED_SOC_H +#define CONFIG_CLOCK_FREQUENCY 10000000 +#define CONFIG_CPU_TYPE_NONE +#define CONFIG_CPU_VARIANT_STANDARD +#define CONFIG_CPU_HUMAN_NAME "Unknown" +#define CONFIG_CSR_DATA_WIDTH 32 +#define CONFIG_CSR_ALIGNMENT 32 +#define CONFIG_BUS_STANDARD "WISHBONE" +#define CONFIG_BUS_DATA_WIDTH 32 +#define CONFIG_BUS_ADDRESS_WIDTH 32 +#define CONFIG_BUS_BURSTING 0 +#define ETHMAC_RX_SLOTS 2 +#define ETHMAC_TX_SLOTS 2 +#define ETHMAC_SLOT_SIZE 2048 + +#ifndef __ASSEMBLER__ +static inline int config_clock_frequency_read(void) { + return 10000000; +} +static inline const char * config_cpu_human_name_read(void) { + return "Unknown"; +} +static inline int config_csr_data_width_read(void) { + return 32; +} +static inline int config_csr_alignment_read(void) { + return 32; +} +static inline const char * config_bus_standard_read(void) { + return "WISHBONE"; +} +static inline int config_bus_data_width_read(void) { + return 32; +} +static inline int config_bus_address_width_read(void) { + return 32; +} +static inline int config_bus_bursting_read(void) { + return 0; +} +static inline int ethmac_rx_slots_read(void) { + return 2; +} +static inline int ethmac_tx_slots_read(void) { + return 2; +} +static inline int ethmac_slot_size_read(void) { + return 2048; +} +#endif // !__ASSEMBLER__ + +#endif diff --git a/gateware/main.py b/gateware/main.py index 1280d5f..5b1884c 100644 --- a/gateware/main.py +++ b/gateware/main.py @@ -16,6 +16,7 @@ import os from memory import * from led import * +from eth import * import i2c import test_i2c @@ -103,6 +104,9 @@ class Core(Elaboratable): m.submodules.uart = uart.UART(10e6) + # Ethernet + m.submodules.eth = LiteEth() + # Counter #m.d.sync += self.count.eq(self.count + 1) #with m.If(self.count >= 50000000): diff --git a/gateware/test.gtwk b/gateware/test.gtwk new file mode 100644 index 0000000..8f63491 --- /dev/null +++ b/gateware/test.gtwk @@ -0,0 +1,3 @@ +[dumpfile] "/home/david/ARVP/sonar_fpga/gateware/test.vcd" +[dumpfile_size] 33226 +[treeopen] top. diff --git a/requirements.txt b/requirements.txt index ac0c1f0..f879280 100644 --- a/requirements.txt +++ b/requirements.txt @@ -2,3 +2,5 @@ git+https://github.com/amaranth-lang/amaranth git+https://github.com/amaranth-lang/amaranth-soc git+https://github.com/minerva-cpu/minerva git+https://github.com/amaranth-community-unofficial/amlib +sphinx +sphinxcontrib-wavedrom