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2 Commits

Author SHA1 Message Date
d207181ef5 gw: increase ROM size 2023-04-15 13:00:06 -06:00
005a053624 fw: testing and fix a couple blocking bugs! 2023-04-15 12:59:54 -06:00
4 changed files with 26 additions and 9 deletions

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@ -1,7 +1,7 @@
MEMORY
{
RAM : ORIGIN = 0x01002000, LENGTH = 4K
FLASH : ORIGIN = 0x01000000, LENGTH = 8K
RAM : ORIGIN = 0x01004000, LENGTH = 4K
FLASH : ORIGIN = 0x01000000, LENGTH = 12K
}
REGION_ALIAS("REGION_TEXT", FLASH);

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@ -44,7 +44,7 @@ impl AmlibI2c{
}
fn is_nack(&self) -> bool {
unsafe { read_reg::<u8>(self.base_addr + SR) & 0x02 != 0 }
unsafe { read_reg::<u8>(self.base_addr + SR) & 0x02 == 0 }
}
}
@ -105,6 +105,10 @@ impl Read<SevenBitAddress> for AmlibI2c {
return Err(Error::Busy);
}
// Set read ACK to 1. Should probably ideally be done in an init() function
// but it doesn't really matter
write_reg(self.base_addr + CR, 0x30u8);
// START
write_reg(self.base_addr + CR, 0x01u8);

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@ -7,6 +7,7 @@ use core::{arch::asm, ptr::{write_volatile, read_volatile}};
use core::fmt::Write;
use embedded_hal::prelude::{_embedded_hal_blocking_i2c_Write, _embedded_hal_blocking_i2c_Read};
use mcp4726::Status;
use riscv_rt::entry;
mod eth;
@ -36,19 +37,31 @@ fn main() -> ! {
//let mut buf = [0u8; 1];
//i2c.read(0b110_0011, &mut buf);
let mut buf = [0u8; 8];
i2c.read(0x63, &mut buf[0..4]).unwrap();
writeln!(uart, "DAC Read before config: {:x}, {:x}, {:x}, {:x}", buf[0], buf[1], buf[2], buf[3]).unwrap();
let mut dac = mcp4726::MCP4726::new(3);
writeln!(uart, "Reading DAC status");
dac.read_status(&mut i2c).unwrap();
writeln!(uart, "Configuring DAC");
writeln!(uart, "Reading DAC status").unwrap();
match dac.read_status(&mut i2c) {
Ok(status) => writeln!(uart, "Is ready? {}, device powered? {}", status.ready, status.device_powered).unwrap(),
Err(e) => {
writeln!(uart, "Error: {:?}", e).unwrap();
panic!();
}
}
writeln!(uart, "Configuring DAC").unwrap();
dac.write_config(&mut i2c, mcp4726::Config {
vref_source: mcp4726::VRef::UnbufferedVRef,
vref_source: mcp4726::VRef::UnbufferedVDD,
operation: mcp4726::PowerDown::NormalOperation,
use_2x_gain: false,
}).unwrap();
writeln!(uart, "Setting DAC");
writeln!(uart, "Setting DAC").unwrap();
dac.write_dac(&mut i2c, 0x0800).unwrap();
i2c.read(0x63, &mut buf[0..4]).unwrap();
writeln!(uart, "DAC Read after config: {:x}, {:x}, {:x}, {:x}", buf[0], buf[1], buf[2], buf[3]).unwrap();
loop {
//eth::tranmsit();
//writeln!(uart, "Hello world!");

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@ -122,7 +122,7 @@ class Core(Elaboratable):
fw = load_firmware_for_mem()
# Hook up memory space
self.rom = ROM(size_bytes=8192, data=fw)
self.rom = ROM(size_bytes=12288, data=fw)
m.submodules.rom = self.rom
# Problem: not sure to handle how we do byte vs word addressing properly
# So doing this shift is a bit of a hacky way to impl anything