david/new-sonar
1
0
Fork 0
Code Issues 11 Pull Requests Projects Releases Wiki Activity

Compare commits

base: david:d207181ef575c668bfc8717484d8fa86e7a2e871
Branches Tags
david:trunk
..
compare: david:b7b556f6d20718dc0fbe4a7852cb42de3b5d75da
Branches Tags
david:trunk

No commits in common. "d207181ef575c668bfc8717484d8fa86e7a2e871" and "b7b556f6d20718dc0fbe4a7852cb42de3b5d75da" have entirely different histories.
d207181ef5 ... b7b556f6d2

4 changed files with 9 additions and 26 deletions
Show Stats Expand all files Collapse all files

4
firmware/memory.x
View File

@ -1,7 +1,7 @@
MEMORY MEMORY
{ {
RAM : ORIGIN = 0x01004000, LENGTH = 4K RAM : ORIGIN = 0x01002000, LENGTH = 4K
FLASH : ORIGIN = 0x01000000, LENGTH = 12K FLASH : ORIGIN = 0x01000000, LENGTH = 8K
} }
REGION_ALIAS("REGION_TEXT", FLASH); REGION_ALIAS("REGION_TEXT", FLASH);

6
firmware/src/i2c.rs
View File

@ -44,7 +44,7 @@ impl AmlibI2c{
} }
fn is_nack(&self) -> bool { fn is_nack(&self) -> bool {
unsafe { read_reg::<u8>(self.base_addr + SR) & 0x02 == 0 } unsafe { read_reg::<u8>(self.base_addr + SR) & 0x02 != 0 }
} }
} }
@ -105,10 +105,6 @@ impl Read<SevenBitAddress> for AmlibI2c {
return Err(Error::Busy); return Err(Error::Busy);
} }
// Set read ACK to 1. Should probably ideally be done in an init() function
// but it doesn't really matter
write_reg(self.base_addr + CR, 0x30u8);
// START // START
write_reg(self.base_addr + CR, 0x01u8); write_reg(self.base_addr + CR, 0x01u8);

23
firmware/src/main.rs
View File

@ -7,7 +7,6 @@ use core::{arch::asm, ptr::{write_volatile, read_volatile}};
use core::fmt::Write; use core::fmt::Write;
use embedded_hal::prelude::{_embedded_hal_blocking_i2c_Write, _embedded_hal_blocking_i2c_Read}; use embedded_hal::prelude::{_embedded_hal_blocking_i2c_Write, _embedded_hal_blocking_i2c_Read};
use mcp4726::Status;
use riscv_rt::entry; use riscv_rt::entry;
mod eth; mod eth;
@ -37,31 +36,19 @@ fn main() -> ! {
//let mut buf = [0u8; 1]; //let mut buf = [0u8; 1];
//i2c.read(0b110_0011, &mut buf); //i2c.read(0b110_0011, &mut buf);
let mut buf = [0u8; 8];
i2c.read(0x63, &mut buf[0..4]).unwrap();
writeln!(uart, "DAC Read before config: {:x}, {:x}, {:x}, {:x}", buf[0], buf[1], buf[2], buf[3]).unwrap();
let mut dac = mcp4726::MCP4726::new(3); let mut dac = mcp4726::MCP4726::new(3);
writeln!(uart, "Reading DAC status").unwrap(); writeln!(uart, "Reading DAC status");
match dac.read_status(&mut i2c) { dac.read_status(&mut i2c).unwrap();
Ok(status) => writeln!(uart, "Is ready? {}, device powered? {}", status.ready, status.device_powered).unwrap(), writeln!(uart, "Configuring DAC");
Err(e) => {
writeln!(uart, "Error: {:?}", e).unwrap();
panic!();
}
}
writeln!(uart, "Configuring DAC").unwrap();
dac.write_config(&mut i2c, mcp4726::Config { dac.write_config(&mut i2c, mcp4726::Config {
vref_source: mcp4726::VRef::UnbufferedVDD, vref_source: mcp4726::VRef::UnbufferedVRef,
operation: mcp4726::PowerDown::NormalOperation, operation: mcp4726::PowerDown::NormalOperation,
use_2x_gain: false, use_2x_gain: false,
}).unwrap(); }).unwrap();
writeln!(uart, "Setting DAC").unwrap(); writeln!(uart, "Setting DAC");
dac.write_dac(&mut i2c, 0x0800).unwrap(); dac.write_dac(&mut i2c, 0x0800).unwrap();
i2c.read(0x63, &mut buf[0..4]).unwrap();
writeln!(uart, "DAC Read after config: {:x}, {:x}, {:x}, {:x}", buf[0], buf[1], buf[2], buf[3]).unwrap();
loop { loop {
//eth::tranmsit(); //eth::tranmsit();
//writeln!(uart, "Hello world!"); //writeln!(uart, "Hello world!");

2
gateware/main.py
View File

@ -122,7 +122,7 @@ class Core(Elaboratable):
fw = load_firmware_for_mem() fw = load_firmware_for_mem()
# Hook up memory space # Hook up memory space
self.rom = ROM(size_bytes=12288, data=fw) self.rom = ROM(size_bytes=8192, data=fw)
m.submodules.rom = self.rom m.submodules.rom = self.rom
# Problem: not sure to handle how we do byte vs word addressing properly # Problem: not sure to handle how we do byte vs word addressing properly
# So doing this shift is a bit of a hacky way to impl anything # So doing this shift is a bit of a hacky way to impl anything