Add 5v->3v3 regulator. #29

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david · 2023-01-23T19:52:19-07:00

david commented

2023-01-23 19:52:19 -07:00

3v3 rail was provided by the Teensy's power regulator. This can likely be served by a beefy linear reg, unless the FPGA carrier board requires significant 3v3 power.

Capable of powering 3v3 rail on fpga carrier
Capable of powering 3v3 rail on preprocessor

3v3 rail was provided by the Teensy's power regulator. This can likely be served by a beefy linear reg, unless the FPGA carrier board requires significant 3v3 power. - [ ] Capable of powering 3v3 rail on fpga carrier - [ ] Capable of powering 3v3 rail on preprocessor

david added the

Hardware

label 2023-01-23 19:52:19 -07:00

david commented

2023-01-23 20:13:08 -07:00

Power Requirements:

4x ADCs (22mA max * 4 = 88mA)
Gain DAC (xxmA, budget 50mA)
I2C pulldowns (worst case 2kOhm, ~4mA)
2.5V Vref (capable of 20mA, so budget that)
Variable clock gen (20mA)

The Colorlight module takes 5V, so does not factor in.

Total requirements: 182mA at max, a 500mA reg is overkill,
but also provides a bit of headroom in case I forgot anything.

Power Requirements: - 4x ADCs (22mA max * 4 = 88mA) - Gain DAC (xxmA, budget 50mA) - I2C pulldowns (worst case 2kOhm, ~4mA) - 2.5V Vref (capable of 20mA, so budget that) - Variable clock gen (20mA) The Colorlight module takes 5V, so does not factor in. Total requirements: 182mA at max, a 500mA reg is overkill, but also provides a bit of headroom in case I forgot anything.

david closed this issue

2023-01-25 16:28:57 -07:00

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