Evaluate and create wishbone interface for amlib I2C device. #6

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opened 2023-01-22 21:07:22 -07:00 by david · 2 comments
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This just means to create a basic wrapper that exposes a few simple wishbone registers.

  • Has tests
  • amlib implementation is sound (or sound enough for what I need)
This just means to create a basic wrapper that exposes a few simple wishbone registers. - [ ] Has tests - [ ] amlib implementation is sound (or sound enough for what I need)
david added the
Gateware
label 2023-01-22 21:07:22 -07:00
david added a new dependency 2023-01-22 21:28:03 -07:00
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Owner

Moving to CSR bus for my peripherals, makes more sense for simpler stuff.

I'll probably still do wishbone for the sampling module, because latency matters more there, but for simple stuff (i.e. I2C and UART) I'll do CSR

Moving to CSR bus for my peripherals, makes more sense for simpler stuff. I'll probably still do wishbone for the sampling module, because latency matters more there, but for simple stuff (i.e. I2C and UART) I'll do CSR
Author
Owner

There's still a couple open questions I have about I2CInitiator/I2CTarget interactions, but I have simulated a full R/W transaction on I2C, so I'm considering this good enough for now, I think any extra problems will come up in bringup.

There's still a couple open questions I have about I2CInitiator/I2CTarget interactions, but I have simulated a full R/W transaction on I2C, so I'm considering this good enough for now, I think any extra problems will come up in bringup.
david closed this issue 2023-01-30 10:13:34 -07:00
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Reference: david/new-sonar#6
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