# Updated Sonar System

This repository contains all the design files for my attempt at an updated and
improved passive sonar data acquisition system. The goal of this system is
simply to be able to capture pinger data, filtered by the preprocessor board,
via ethernet, at significantly faster speed than the previous system.

## Pysonar

This provides a library to interface with the FPGA, both pulling data and configuring it. To install, simply `cd`
into this repo and:

```shell
pip install ./
```

A CLI/console to test configuration is provided as `sonar_config`. Usage can be found with

```shell
sonar_config --help
```

*Note: This is a pure python package. In an ideal world, I would have implemented all protocol
implementation in rust, and exported via PyO3, to keep potential changes in sync, but it's not
worth the implementation effort and potential installation difficulty here.*

## Hacky hacks to patch into migen

migen.fhdl.simplify.py (line 81): add the attributeerror exception

```
          for port in mem.ports:
                try:
                    sync = f.sync[port.clock.cd]
                except KeyError:
                    sync = f.sync[port.clock.cd] = []
                except AttributeError:
                    sync = f.sync["sys"]
```

## Repo Layout

```
firmware/
  hello_world_c - My very first testing code for doing SoC bringup
  TODO - break FW out into multiple crates to provide more functionality
gateware/ - RTL for creating the SoC
hardware/ - Directory for any hardware designs
  pmod/ - A PMOD interface board, using 4 ADCs with LVDS converters to get data across PMOD [Failed Idea]
  colorlight-base/ - Baseboard that attaches to the preprocessor (replases BeagleBone + PruDAQ)
  sonar-footprints.pretty/ - custom KiCAD footprints for this project
  sonar_symbols.kicad_sym - custom KiCAD symbols I create for hardware
  colorlight_pin_extractor.py - a script I used to help in making the kicad symbol for the colorlight module
```

## Design Goals

- ~~4x 20MSPS channels @ > 8 bits~~ Reduced to 10MSPS @ 9 bits due to memory resource constraints.
- Ethernet data channel
- Simplified software stack (or at least fewer layers of components)
- Well-documented

## RTL Architecture

General SoC architecture and other similar goodies can be found in
`gateware/docs`.

To over simplify, I am creating an SoC with an rv32im core, connected to a
single wishbone bus to access all memory and peripherals. All RTL is written in
Amaranth.

## Firmware Architecture

Given how much I can very simply offload onto the RTL (peak detection, maaaybe DMA, etc.),
the firmware will be pretty simple. I will use embassy just to make things easier
on myself. All I really have to do is provide some configuration interface over ethernet,
set up and read out captures, and push those to the Xavier.

The configuration interface only needs to expose the following functionality:

- Stop/start capturing
- Set filter frequency
- Set capture size and offset
- Automatic triggering settings
- Manual triggering

The data channel can be whatever form I want, although if ZMQ is easy to
implement I may keep it to reduce changes to the ROS software.

## Random notes

You will probably need to un write-protect the flash on the colorlight

Will *not* be doing LVDS system, because arty doesn't have selectable bank
voltage to actually use it.

Switching to use Colorlight i9 board (ECP5 UP5K 45), because it has plenty IO
broken out, also provides ethernet (I just need to implement the magnetics and
jack), and is cheaper/potentially easier to acquire for ARVP in the future. The
LiteX implementation fits in <40% of total resources of the 25K LUT variant, so
the 45K should be plenty for what I need. Frankly what I'm implementing is very
simple. It can probably even handle doing the FFT on board if I wanted to.

### ecpdap: "Error: specified probe not found"

A Reboot fixed it....

Do I have ecpdap installed in two places and one of them doesn't work maybe?

I do have two versions installed. one from oss-cad-suite and one by building it
manually.