from amaranth import *
from amaranth_soc.wishbone.bus import Interface

# TODO maybe this should just call liteeth_gen to close the loop?
class LiteEth(Elaboratable, Interface):
    def __init__(self):

        # TODO change ADDR width
        Interface.__init__(self, addr_width=32, data_width=32)

        self.rgmii_eth_clocks_tx = Signal()


    def elaborate(self, platform):
        platform.add_file("liteeth_core.v", open("liteeth/gateware/liteeth_core.v", 'r').read())

        m = Module()

        core = Instance(
            "liteeth_core",
            i_sys_clock=ClockSignal(),
            o_rgmii_eth_clocks_tx=self.rgmii_eth_clocks_tx,
        )

        m.submodules.core = core

        return m