#!/usr/bin/env python3 # # This file is part of LiteX-Boards. # # Copyright (c) 2021 Kazumoto Kojima # SPDX-License-Identifier: BSD-2-Clause from migen import * from litex.build.io import DDROutput from platforms import sonar as colorlight_i5 from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.video import VideoHDMIPHY from litex.soc.cores.led import LedChaser from litex.soc.interconnect.csr import * from litedram.modules import M12L64322A # Compatible with EM638325-6H. from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII from sampler import SamplerController, Sampler from litex.soc.integration.soc import SoCRegion from test import run_test, TestResult, skip_suite # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform, sys_clk_freq, use_internal_osc=False, with_usb_pll=False, with_video_pll=False, sdram_rate="1:1"): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain("sys") self.clock_domains.cd_sample_clock = ClockDomain("sample_clock") if sdram_rate == "1:2": self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x_ps = ClockDomain() else: self.clock_domains.cd_sys_ps = ClockDomain("sys_ps") # # # # Clk / Rst if not use_internal_osc: clk = platform.request("clk25") clk_freq = 25e6 else: clk = Signal() div = 5 self.specials += Instance("OSCG", p_DIV = div, o_OSC = clk ) clk_freq = 310e6/div #rst_n = platform.request("cpu_reset_n") # PLL self.submodules.pll = pll = ECP5PLL() self.comb += pll.reset.eq(self.rst) pll.register_clkin(clk, clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq) if sdram_rate == "1:2": pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased. else: pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) # Idealy 90° but needs to be increased. # SDRAM clock sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk) # Sampler clock pll.create_clkout(self.cd_sample_clock, int(10e6)) # BaseSoC ------------------------------------------------------------------------------------------ # TODO make my own platform for this based on the colorlight one, so I can export I2C and other pins class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=60e6, eth_phy=0, with_led_chaser=True, use_internal_osc=False, sdram_rate="1:1", with_video_terminal=False, with_video_framebuffer=False, **kwargs): # TODO change SRAM size kwargs["integrated_sram_size"] = 64 * 1024 kwargs["integrated_rom_init"] = "../firmware/fw.bin" platform = colorlight_i5.Platform(board="i9", revision="7.2", toolchain="trellis") # CRG -------------------------------------------------------------------------------------- with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" with_video_pll = with_video_terminal or with_video_framebuffer self.submodules.crg = _CRG(platform, sys_clk_freq, use_internal_osc = use_internal_osc, with_usb_pll = with_usb_pll, with_video_pll = with_video_pll, sdram_rate = sdram_rate ) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, int(sys_clk_freq), ident = "LiteX SoC on Sonar FPGA", **kwargs) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: ledn = platform.request_all("user_led_n") self.submodules.leds = LedChaser(pads=ledn, sys_clk_freq=sys_clk_freq) # SPI Flash -------------------------------------------------------------------------------- from litespi.modules import W25Q64 as SpiFlashModule from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="1x", module=SpiFlashModule(Codes.READ_1_1_1)) # SDR SDRAM -------------------------------------------------------------------------------- #if not self.integrated_main_ram_size: # sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY # self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) # self.add_sdram("sdram", # phy = self.sdrphy, # module = M12L64322A(sys_clk_freq, sdram_rate), # l2_cache_size = kwargs.get("l2_size", 8192) # ) # Ethernet / Etherbone --------------------------------------------------------------------- self.submodules.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks", eth_phy), pads = self.platform.request("eth", eth_phy), tx_delay = 0) self.add_ethernet(phy=self.ethphy) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"), clock_domain="hdmi") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi") #samplers = [Sampler(platform.request("adc", i)) for i in range(3)] #self.submodules.sampler_controller = SamplerController(samplers, buffer_len=2048 * 10) ### TODO better way to do this? #sampler_region = SoCRegion(origin=None, size=0x4000, cached=False) #self.bus.add_slave(name="sampler", slave=self.sampler_controller.bus, region=sampler_region) # Build -------------------------------------------------------------------------------------------- def main(): from litex.soc.integration.soc import LiteXSoCArgumentParser parser = LiteXSoCArgumentParser(description="LiteX SoC on Colorlight I5") target_group = parser.add_argument_group(title="Target options") target_group.add_argument("--build", action="store_true", help="Build design.") target_group.add_argument("--load", action="store_true", help="Load bitstream.") target_group.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency.") sdopts = target_group.add_mutually_exclusive_group() sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.") target_group.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).") target_group.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator.") target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).") viopts = target_group.add_mutually_exclusive_group() viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).") viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).") testopts = parser.add_argument_group(title="Testing Options") testopts.add_argument("--test", action="store_true", help="Run tests, won't do anything else") builder_args(parser) soc_core_args(parser) trellis_args(parser) args = parser.parse_args() # Run tests first if args.test: from sampler import circular_buffer from sampler import controller from sampler import peak_detector results = [] results.append(run_test("CircularBuffer", circular_buffer.testbench)) results.append(run_test("SamplerController", controller.test_bus_access)) results.append(run_test("SamplerController", controller.test_simple_waveform)) results.append(run_test("SamplerController", controller.test_simple_waveform_capture_offset)) results.append(run_test("SamplerController", controller.test_multiple_reads)) results.append(run_test("PeakDetector", peak_detector.test_simple_waveform)) results.append(run_test("PeakDetector", peak_detector.test_scrunched_simple_waveform)) results.append(run_test("PeakDetector", peak_detector.test_decay_simple_waveform)) results.append(run_test("PeakDetector", peak_detector.test_decay_simple_waveform_too_much)) results.append(run_test("PeakDetector", peak_detector.test_decay_compensates_bias)) results.append(run_test("PeakDetector", peak_detector.test_biased_simple_waveform)) results.append(run_test("PeakDetector", peak_detector.test_noise_spike)) passed = sum((1 for result in results if result.result == TestResult.PASS)) failed = sum((1 for result in results if result.result == TestResult.FAIL)) skipped = sum((1 for result in results if result.result == TestResult.SKIP)) print(f"{passed}/{passed + failed} passed ({skipped} skipped)") if failed > 0 or not args.build: # Don't also build after this return # Build firmware import subprocess as sp sp.run(["./build_and_strip.sh"], cwd="../firmware").check_returncode() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), eth_phy = args.eth_phy, use_internal_osc = args.use_internal_osc, sdram_rate = args.sdram_rate, with_video_terminal = args.with_video_terminal, with_video_framebuffer = args.with_video_framebuffer, **soc_core_argdict(args) ) soc.platform.add_extension(colorlight_i5._sdcard_pmod_io) if args.with_spi_sdcard: soc.add_spi_sdcard() if args.with_sdcard: soc.add_sdcard() builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.build: builder.build(**builder_kargs) if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(builder.get_bitstream_filename(mode="sram")) if __name__ == "__main__": main()