.. wavedrom::
    :caption: CTRL_RESET

    {
        "reg": [
            {"name": "soc_rst",  "type": 4, "bits": 1},
            {"name": "cpu_rst",  "bits": 1},
            {"bits": 30}
        ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4}
    }

<div style="overflow-x:auto">
<script type="WaveDrom">
{
    "reg": [
        {"name": "soc_rst",  "type": 4, "bits": 1},
        {"name": "cpu_rst",  "bits": 1},
        {"bits": 30}
    ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4}
}
</script>
</div>

Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset)

Use this register as a scratch space to verify that software read/write accesses
to the Wishbone/CSR bus are working correctly. The initial reset value of
0x1234578 can be used to verify endianness.

    :caption: CTRL_SCRATCH

    {
        "reg": [
            {"name": "scratch[31:0]", "attr": 'reset: 305419896', "bits": 32}
        ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1}
    }

{
    "reg": [
        {"name": "scratch[31:0]", "attr": 'reset: 305419896', "bits": 32}
    ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1}
}
</script>
</div>

Total number of Wishbone bus errors (timeouts) since start.

    :caption: CTRL_BUS_ERRORS

    {
        "reg": [
            {"name": "bus_errors[31:0]", "bits": 32}
    }

{
    "reg": [
        {"name": "bus_errors[31:0]", "bits": 32}
}
</script>
</div>

    :caption: ETHMAC_SRAM_WRITER_SLOT

    {
        "reg": [
            {"name": "sram_writer_slot", "bits": 1},
            {"bits": 31},
    }

{
    "reg": [
        {"name": "sram_writer_slot", "bits": 1},
        {"bits": 31},
}
</script>
</div>

    :caption: ETHMAC_SRAM_WRITER_LENGTH

    {
        "reg": [
            {"name": "sram_writer_length[10:0]", "bits": 11},
            {"bits": 21},
    }

{
    "reg": [
        {"name": "sram_writer_length[10:0]", "bits": 11},
        {"bits": 21},
}
</script>
</div>

    :caption: ETHMAC_SRAM_WRITER_ERRORS

    {
        "reg": [
            {"name": "sram_writer_errors[31:0]", "bits": 32}
    }

{
    "reg": [
        {"name": "sram_writer_errors[31:0]", "bits": 32}
}
</script>
</div>

This register contains the current raw level of the available event trigger.
Writes to this register have no effect.

    :caption: ETHMAC_SRAM_WRITER_EV_STATUS

    {
        "reg": [
            {"name": "available",  "bits": 1},
            {"bits": 31}
    }

{
    "reg": [
        {"name": "available",  "bits": 1},
        {"bits": 31}
}
</script>
</div>

When a  available event occurs, the corresponding bit will be set in this
register.  To clear the Event, set the corresponding bit in this register.

    :caption: ETHMAC_SRAM_WRITER_EV_PENDING

    {
        "reg": [
    }

`1` if a `available` event occurred. This Event is **level triggered** when the
signal is **high**.

This register enables the corresponding available events.  Write a ``0`` to this
register to disable individual events.

    :caption: ETHMAC_SRAM_WRITER_EV_ENABLE

    {
        "reg": [
    }

This register enables the corresponding available events.  Write a 

    :caption: ETHMAC_SRAM_READER_START

    {
        "reg": [
            {"name": "sram_reader_start", "bits": 1},
    }

{
    "reg": [
        {"name": "sram_reader_start", "bits": 1},
}
</script>
</div>

    :caption: ETHMAC_SRAM_READER_READY

    {
        "reg": [
            {"name": "sram_reader_ready", "bits": 1},
    }

{
    "reg": [
        {"name": "sram_reader_ready", "bits": 1},
}
</script>
</div>

    :caption: ETHMAC_SRAM_READER_LEVEL

    {
        "reg": [
            {"name": "sram_reader_level[1:0]", "bits": 2},
            {"bits": 30},
    }

{
    "reg": [
        {"name": "sram_reader_level[1:0]", "bits": 2},
        {"bits": 30},
}
</script>
</div>

    :caption: ETHMAC_SRAM_READER_SLOT

    {
        "reg": [
            {"name": "sram_reader_slot", "bits": 1},
    }

{
    "reg": [
        {"name": "sram_reader_slot", "bits": 1},
}
</script>
</div>

    :caption: ETHMAC_SRAM_READER_LENGTH

    {
        "reg": [
            {"name": "sram_reader_length[10:0]", "bits": 11},
    }

{
    "reg": [
        {"name": "sram_reader_length[10:0]", "bits": 11},
}
</script>
</div>

This register contains the current raw level of the event0 event trigger.

    :caption: ETHMAC_SRAM_READER_EV_STATUS

    {
        "reg": [
            {"name": "event0",  "bits": 1},
    }

{
    "reg": [
        {"name": "event0",  "bits": 1},
}
</script>
</div>

When a  event0 event occurs, the corresponding bit will be set in this register.
To clear the Event, set the corresponding bit in this register.

    :caption: ETHMAC_SRAM_READER_EV_PENDING

    {
        "reg": [
    }

`1` if a this particular event occurred. This Event is triggered on a **rising**
edge.

 if a this particular event occurred. This Event is triggered on a 

This register enables the corresponding event0 events.  Write a ``0`` to this

    :caption: ETHMAC_SRAM_READER_EV_ENABLE

    {
        "reg": [
    }

This register enables the corresponding event0 events.  Write a 

    :caption: ETHMAC_PREAMBLE_CRC

    {
        "reg": [
            {"name": "preamble_crc", "attr": 'reset: 1', "bits": 1},
    }

{
    "reg": [
        {"name": "preamble_crc", "attr": 'reset: 1', "bits": 1},
}
</script>
</div>

    :caption: ETHMAC_RX_DATAPATH_PREAMBLE_ERRORS

    {
        "reg": [
            {"name": "rx_datapath_preamble_errors[31:0]", "bits": 32}
    }

{
    "reg": [
        {"name": "rx_datapath_preamble_errors[31:0]", "bits": 32}
}
</script>
</div>

    :caption: ETHMAC_RX_DATAPATH_CRC_ERRORS

    {
        "reg": [
            {"name": "rx_datapath_crc_errors[31:0]", "bits": 32}
    }

{
    "reg": [
        {"name": "rx_datapath_crc_errors[31:0]", "bits": 32}
}
</script>
</div>

    :caption: ETHPHY_CRG_RESET

    {
        "reg": [
            {"name": "crg_reset", "bits": 1},
    }

{
    "reg": [
        {"name": "crg_reset", "bits": 1},
}
</script>
</div>

    :caption: ETHPHY_RX_INBAND_STATUS

    {
        "reg": [
            {"name": "link_status",  "bits": 1},
            {"name": "clock_speed",  "bits": 1},
            {"name": "duplex_status",  "bits": 1},
            {"bits": 29}
    }

{
    "reg": [
        {"name": "link_status",  "bits": 1},
        {"name": "clock_speed",  "bits": 1},
        {"name": "duplex_status",  "bits": 1},
        {"bits": 29}
}
</script>
</div>

    :caption: ETHPHY_MDIO_W

    {
        "reg": [
            {"name": "mdc",  "bits": 1},
            {"name": "oe",  "bits": 1},
            {"name": "w",  "bits": 1},
    }

{
    "reg": [
        {"name": "mdc",  "bits": 1},
        {"name": "oe",  "bits": 1},
        {"name": "w",  "bits": 1},
}
</script>
</div>

    :caption: ETHPHY_MDIO_R

    {
        "reg": [
            {"name": "r",  "bits": 1},
    }

{
    "reg": [
        {"name": "r",  "bits": 1},
}
</script>
</div>

This device has an ``EventManager``-based interrupt system.  Individual modules
generate `events` which are wired into a central interrupt controller.

When an interrupt occurs, you should look the interrupt number up in the CPU-
specific interrupt table and then call the relevant module.

+-----------+--------+
| Interrupt | Module |
+===========+========+