`default_nettype none

module led_gpio #(
    parameter DATA_WIDTH = 32,
    parameter ADR_WIDTH = 32,
    parameter SEL_WIDTH = 4 // ???
) (
    // Main signals
    input wire clk,
    input wire rst,

    // verilator lint_off UNUSED
    // ----  LiteX Wishbone interface
    // Address
    input wire [ADR_WIDTH-1:0] adr,
    // Data input (write)
    input wire [DATA_WIDTH-1:0] dat_w,
    // Data output (read)
    output reg [DATA_WIDTH-1:0] dat_r,
    // What parts of data are valid?
    input wire [SEL_WIDTH-1:0] sel,
    // Start cycle
    input wire cyc,
    // Enables wishbone interface
    input wire stb,
    // Bus cycle finished
    output reg ack,
    // Is this cycle a read or write?
    input wire we,
    // Cycle type
    input wire [2:0] cti,
    // Burst type
    input wire [1:0] bte,
    // Asserted if cycle completes with error
    output wire err,
    // verilator lint_on UNUSED

    // Output
    output wire led
);

// Tracks if we have started a new wishbone cycle. This or similar is needed so we don't
// think we're handling multiple wishbone cycles inside one.
reg cycle_started;
reg led_state;

always @(posedge clk) begin
    // Always reset the cycle started
    cycle_started <= 0;

    if (rst) begin
        led_state <= 0;
    end else begin
        // TODO ADR checking
        ack <= 0;
        err <= 0; // We never have any bus errors
        dat_r <= 0;

        if (!cycle_started && stb && cyc) begin
            cycle_started <= 1; // Start cycle to be reset next clock
            ack <= 1; // We always acknowledge immediately, we only take one clock to process

            if (we) begin
                // Writes to LED, so we need to assign output
                led_state <= dat_w[0];
            end else begin
                // We want reads to get LED status
                dat_r <= 3;
            end
        end
    end
end

always @(*) begin
    led = !led_state;
end

endmodule

`default_nettype wire