from migen import *
from migen.genlib.cdc import PulseSynchronizer


class Sampler(Module):
    def __init__(self, adc_pins: Record, sampler_clock: Signal):
        # self.clock_domains.foo = ClockDomain() is how to add a new clock domain, accessible at self.foo
        # Connect sampler clock domain
        self.clock_domains.sample_clock = ClockDomain("sample_clock")
        self.comb += self.sample_clock.clk.eq(sampler_clock)

        # Hook up ADC REFCLK to sample_clock
        self.comb += adc_pins.refclk.eq(sampler_clock)

        # We can synchronize to the sampler clock, whenever it goes high we can
        # strobe a single valid signal
        synchronizer = PulseSynchronizer("sample_clock", "sys")
        self.submodules += synchronizer

        self.valid = Signal()
        self.data = Signal(10)

        self.comb += [
            synchronizer.i.eq(self.sample_clock.clk),
            self.valid.eq(synchronizer.o),
            self.data.eq(adc_pins.data),
        ]

        # Set config pins to constant values
        self.comb += adc_pins.oen_b.eq(0)       # Data pins enable
        self.comb += adc_pins.standby.eq(0)     # Sampling standby
        self.comb += adc_pins.dfs.eq(0)         # DFS (raw or two's complement)
        # The only remaining pin, OTR, is an out of range status indicator