diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 0865e76..c16db10 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -35,6 +35,8 @@ class _Value(DUID):
                 return a.value == b.value
             if isinstance(a, Signal) and isinstance(b, Signal):
                 return a is b
+            if isinstance(a, ClockSignal) and isinstance(b, ClockSignal):
+                return a.cd == b.cd
             if (isinstance(a, Constant) and isinstance(b, Signal)
                     or isinstance(a, Signal) and isinstance(b, Constant)):
                 return False
diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 9bde3de..379c52f 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -56,6 +56,8 @@ def _printexpr(ns, node):
         return _printconstant(node)
     elif isinstance(node, Signal):
         return ns.get_name(node), node.signed
+    elif isinstance(node, ClockSignal):
+        return ns.get_name(node), False
     elif isinstance(node, _Operator):
         arity = len(node.operands)
         r1, s1 = _printexpr(ns, node.operands[0])