#!/usr/bin/env python3

# General imports
from migen import *

from litex.build.io import DDROutput

from litex_boards.platforms import colorlight_i5

from litex.build.lattice.trellis import trellis_args, trellis_argdict

from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *

from litex.soc.interconnect.csr import *

from litex.soc.interconnect import wishbone
from litex.soc.integration.soc import SoCRegion

from litedram.modules import M12L64322A
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY

from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII

# My hardware
import led_gpio

# Module to configure clocks and resets
class _CRG(Module):
    def __init__(self, platform, sys_clk_freq, use_internal_osc=False, with_usb_pll=False, with_video_pll=False, sdram_rate="1:1"):
        self.rst = Signal()
        self.clock_domains.cd_sys    = ClockDomain()
        if sdram_rate == "1:2":
            self.clock_domains.cd_sys2x    = ClockDomain()
            self.clock_domains.cd_sys2x_ps = ClockDomain()
        else:
            self.clock_domains.cd_sys_ps = ClockDomain()

        # # #

        # Clk / Rst
        if not use_internal_osc:
            clk = platform.request("clk25")
            clk_freq = 25e6
        else:
            clk = Signal()
            div = 5
            self.specials += Instance("OSCG",
                p_DIV = div,
                o_OSC = clk
            )
            clk_freq = 310e6/div

        rst_n = platform.request("cpu_reset_n")

        # PLL
        self.submodules.pll = pll = ECP5PLL()
        self.comb += pll.reset.eq(~rst_n | self.rst)
        pll.register_clkin(clk, clk_freq)
        pll.create_clkout(self.cd_sys,    sys_clk_freq)
        if sdram_rate == "1:2":
            pll.create_clkout(self.cd_sys2x,    2*sys_clk_freq)
            pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
        else:
           pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.

        # USB PLL
        if with_usb_pll:
            self.submodules.usb_pll = usb_pll = ECP5PLL()
            self.comb += usb_pll.reset.eq(~rst_n | self.rst)
            usb_pll.register_clkin(clk, clk_freq)
            self.clock_domains.cd_usb_12 = ClockDomain()
            self.clock_domains.cd_usb_48 = ClockDomain()
            usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
            usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0)

        # Video PLL
        if with_video_pll:
            self.submodules.video_pll = video_pll = ECP5PLL()
            self.comb += video_pll.reset.eq(~rst_n | self.rst)
            video_pll.register_clkin(clk, clk_freq)
            self.clock_domains.cd_hdmi   = ClockDomain()
            self.clock_domains.cd_hdmi5x = ClockDomain()
            video_pll.create_clkout(self.cd_hdmi,    40e6, margin=0)
            video_pll.create_clkout(self.cd_hdmi5x, 200e6, margin=0)

        # SDRAM clock
        sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
        self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)


# SoC definition - this basically instantiates hardware
class SoC(SoCCore):

    csr_peripherals = ["led_gpio"]
    #csr_map_update(SoCCore.csr_map, csr_peripherals)

    # While there are more configurations in what I'm basing this off of, I'm reducing it to
    # one supported config.
    def __init__(self, **kwargs):
        platform = colorlight_i5.Platform(board="i9", revision = "7.2", toolchain="trellis")

        sys_clk_freq = 50e6

        self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate="1:1")

        # Initialize base SoC core stuff, with given system clock
        SoCCore.__init__(self, platform, int(sys_clk_freq), ident = "Sonar SoC on Colorlight i9", **kwargs)

        # Set SPI flash with correct configuration
        from litespi.modules import W25Q64 as SpiFlashModule
        from litespi.opcodes import SpiNorFlashOpCodes as Codes
        # 1x SPI interface (as opposed to QSPI or something), and use the simplest READ timing commands
        self.add_spi_flash(mode="1x", module=SpiFlashModule(Codes.READ_1_1_1))

        # Set up SDRAM
        sdrphy_cls = GENSDRPHY
        self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
        self.add_sdram("sdram",
            phy = self.sdrphy,
            module = M12L64322A(sys_clk_freq, "1:1"),
            l2_cache_size = 8192,
        )

        # LED blinky thing
        #wb_interface = wishbone.Interface()
        led = platform.request("user_led_n")
        self.submodules.led_gpio = led_gpio.LedGpio(platform, led)
        #wb_interface.connect_to_pads(led, mode="slave")

        #self.add_memory_region("led_gpio", 0x8F000000, 0x1000, type="dawda")
        #self.add_wb_slave(0x8F000000, wb_interface, 0x1000)

        # vague attempt based on 
        #region = SoCRegion(origin=0x8F000000, size=0x1000, cached=False)
        #self.bus.add_slave(name="led_gpio", slave=wb_interface, region=region)

        # TODO ethernet


def main():
    from litex.soc.integration.soc import LiteXSoCArgumentParser
    parser = LiteXSoCArgumentParser(description="LiteX SoC for FPGA sonar")
    target_group = parser.add_argument_group(title="Target options")
    target_group.add_argument("--build", action="store_true", help="Build design")
    target_group.add_argument("--load", action="store_true", help="Load design onto board")
    builder_args(parser)
    soc_core_args(parser)
    trellis_args(parser)
    args = parser.parse_args()

    soc = SoC(**soc_core_argdict(args))

    builder = Builder(soc, **builder_argdict(args))
    builder_kargs = trellis_argdict(args)
    if args.build:
        builder.build(**builder_kargs)

    if args.load:
        prog = soc.platform.create_programmer()
        prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))


if __name__ == "__main__":
    main()