# Updated Sonar System

## Repo Layout

```
hardware/ - Directory for any hardware designs
  pmod/ - A PMOD interface board, using 4 ADCs with LVDS converters to get data across PMOD
```

## Design Goals

- 4x 20MSPS channels @ > 8 bits
- Ethernet data channel
- Simplified software stack (or at least fewer layers of components)
- Well-documented

## System Architecture

<!-- made with asciiflow.com -->
```
┌─────────────┐
│Main Computer│
└─────▲───────┘
      │
      │
      │
┌─────┴──────┐
│Ethernet PHY│
│      ▲     │           Interface Board (x4)
│      │     │       ┌──────────────────────────────┐
│      │     │       │                              │            ┌─────────────┐
│      │     │◄──────┤ LVDS Serializer◄─────────ADC │◄───────────┤ Hydrophones │
│      │     │       │                              │            └─────────────┘
│      │     │       └──────────────────────────────┘
│    FPGA    │
└─────▲──────┘
      │ Dev Board
      │ or
      │ Custom Board
      │
      │
      │
   ┌──┴───────────────────┐
   │ Peak Detector Board  │
   └──────────────────────┘
               (Temporary)
```

## RTL Architecture

#### Diagram TODO

The plan is to use LiteX and let it do most of the heavy lifting. Components to
generate:

- Softcore (some RISC-V core)
- Main memory bus
- DMA engine
- Gigabit Ethernet MAC

THis way the only actual RTL to write is the peripheral that interacts with the ADCs,
which should be very simple. To do early bringup I can start with a blinky peripheral to
demonstrate access to the bus, and then I can keep adding functionality.

## Software Planning

Will try to use embassy on RISC-V if I can.

Should make sure to have a debug port available as early as possible.

I will make the interface as generic as possible, so it should be easy to swap out, but I
will start by targetting zmq so I can change as little of the software stack as possible.