ETHMAC

Register Listing for ETHMAC

Register	Address
ETHMAC_SRAM_WRITER_SLOT	0x00000800
ETHMAC_SRAM_WRITER_LENGTH	0x00000804
ETHMAC_SRAM_WRITER_ERRORS	0x00000808
ETHMAC_SRAM_WRITER_EV_STATUS	0x0000080c
ETHMAC_SRAM_WRITER_EV_PENDING	0x00000810
ETHMAC_SRAM_WRITER_EV_ENABLE	0x00000814
ETHMAC_SRAM_READER_START	0x00000818
ETHMAC_SRAM_READER_READY	0x0000081c
ETHMAC_SRAM_READER_LEVEL	0x00000820
ETHMAC_SRAM_READER_SLOT	0x00000824
ETHMAC_SRAM_READER_LENGTH	0x00000828
ETHMAC_SRAM_READER_EV_STATUS	0x0000082c
ETHMAC_SRAM_READER_EV_PENDING	0x00000830
ETHMAC_SRAM_READER_EV_ENABLE	0x00000834
ETHMAC_PREAMBLE_CRC	0x00000838
ETHMAC_RX_DATAPATH_PREAMBLE_ERRORS	0x0000083c
ETHMAC_RX_DATAPATH_CRC_ERRORS	0x00000840

ETHMAC_SRAM_WRITER_SLOT

Address: 0x00000800 + 0x0 = 0x00000800

ETHMAC_SRAM_WRITER_LENGTH

Address: 0x00000800 + 0x4 = 0x00000804

ETHMAC_SRAM_WRITER_ERRORS

Address: 0x00000800 + 0x8 = 0x00000808

ETHMAC_SRAM_WRITER_EV_STATUS

Address: 0x00000800 + 0xc = 0x0000080c

This register contains the current raw level of the available event trigger. Writes to this register have no effect.

Field	Name	Description
[0]	AVAILABLE	Level of the available event

ETHMAC_SRAM_WRITER_EV_PENDING

Address: 0x00000800 + 0x10 = 0x00000810

When a available event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register.

Field	Name	Description
[0]	AVAILABLE	1 if a available event occurred. This Event is level triggered when the signal is high.

ETHMAC_SRAM_WRITER_EV_ENABLE

Address: 0x00000800 + 0x14 = 0x00000814

This register enables the corresponding available events. Write a 0 to this register to disable individual events.

Field	Name	Description
[0]	AVAILABLE	Write a 1 to enable the available Event

ETHMAC_SRAM_READER_START

Address: 0x00000800 + 0x18 = 0x00000818

ETHMAC_SRAM_READER_READY

Address: 0x00000800 + 0x1c = 0x0000081c

ETHMAC_SRAM_READER_LEVEL

Address: 0x00000800 + 0x20 = 0x00000820

ETHMAC_SRAM_READER_SLOT

Address: 0x00000800 + 0x24 = 0x00000824

ETHMAC_SRAM_READER_LENGTH

Address: 0x00000800 + 0x28 = 0x00000828

ETHMAC_SRAM_READER_EV_STATUS

Address: 0x00000800 + 0x2c = 0x0000082c

This register contains the current raw level of the event0 event trigger. Writes to this register have no effect.

Field	Name	Description
[0]	EVENT0	Level of the event0 event

ETHMAC_SRAM_READER_EV_PENDING

Address: 0x00000800 + 0x30 = 0x00000830

When a event0 event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register.

Field	Name	Description
[0]	EVENT0	1 if a this particular event occurred. This Event is triggered on a rising edge.

ETHMAC_SRAM_READER_EV_ENABLE

Address: 0x00000800 + 0x34 = 0x00000834

This register enables the corresponding event0 events. Write a 0 to this register to disable individual events.

Field	Name	Description
[0]	EVENT0	Write a 1 to enable the event0 Event

ETHMAC_PREAMBLE_CRC

Address: 0x00000800 + 0x38 = 0x00000838

ETHMAC_RX_DATAPATH_PREAMBLE_ERRORS

Address: 0x00000800 + 0x3c = 0x0000083c

ETHMAC_RX_DATAPATH_CRC_ERRORS

Address: 0x00000800 + 0x40 = 0x00000840