David Lenfesty
5b62dd300b
Still unclear what exactly this fixes, I think mostly bugs in migen/LiteX. Not sure if it's synthesizing the memory elements for the sampler modules either.
29 lines
1.0 KiB
Python
29 lines
1.0 KiB
Python
from migen import *
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from migen.genlib.cdc import PulseSynchronizer
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class Sampler(Module):
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def __init__(self, adc_pins: Record):
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# Hook up ADC REFCLK to sample_clock
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self.comb += adc_pins.refclk.eq(ClockDomain("sample_clock").clk)
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# We can synchronize to the sampler clock, whenever it goes high we can
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# strobe a single valid signal
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synchronizer = PulseSynchronizer("sample_clock", "sys")
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self.submodules += synchronizer
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self.valid = Signal()
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self.data = Signal(10)
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self.comb += [
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synchronizer.i.eq(ClockDomain("sample_clock").clk),
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self.valid.eq(synchronizer.o),
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]
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self.sync += self.data.eq(adc_pins.data)
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# Set config pins to constant values
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self.comb += adc_pins.oen_b.eq(0) # Data pins enable
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self.comb += adc_pins.standby.eq(0) # Sampling standby
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self.comb += adc_pins.dfs.eq(0) # DFS (raw or two's complement)
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# The only remaining pin, OTR, is an out of range status indicator
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