27 lines
1.1 KiB
Diff
Executable File
27 lines
1.1 KiB
Diff
Executable File
diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
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index 0865e76..c16db10 100644
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--- a/migen/fhdl/structure.py
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+++ b/migen/fhdl/structure.py
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@@ -35,6 +35,8 @@ class _Value(DUID):
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return a.value == b.value
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if isinstance(a, Signal) and isinstance(b, Signal):
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return a is b
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+ if isinstance(a, ClockSignal) and isinstance(b, ClockSignal):
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+ return a.cd == b.cd
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if (isinstance(a, Constant) and isinstance(b, Signal)
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or isinstance(a, Signal) and isinstance(b, Constant)):
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return False
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diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
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index 9bde3de..379c52f 100644
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--- a/migen/fhdl/verilog.py
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+++ b/migen/fhdl/verilog.py
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@@ -56,6 +56,8 @@ def _printexpr(ns, node):
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return _printconstant(node)
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elif isinstance(node, Signal):
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return ns.get_name(node), node.signed
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+ elif isinstance(node, ClockSignal):
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+ return ns.get_name(node), False
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elif isinstance(node, _Operator):
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arity = len(node.operands)
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r1, s1 = _printexpr(ns, node.operands[0])
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