421 lines
14 KiB
Python
421 lines
14 KiB
Python
from migen import *
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from litex.soc.interconnect.wishbone import *
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from math import ceil, log2
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from typing import List
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from .sampler import Sampler
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from .circular_buffer import CircularBuffer
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from .peak_detector import PeakDetector
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class SamplerController(Module):
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"""
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Sampler control
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Attributes
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----------
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bus:
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Slave wishbone bus to be connected to a higher-level bus. Has an address width set according to
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the provided buffer length.
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buffers:
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List of FIFO buffer objects used to store sample data.
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samplers:
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List of sampler objects provided by user.
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Registers
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--------
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0x00: Control Register (RW)
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Bit 0 - Begin capture. Resets all FIFOs and starts the peak detector
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0x01: Status Register (RO)
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Bit 0 - Capture complete. Set by peak detection block and cleared when capture is began
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0x02: trigger_run_len (RW)
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Number of samples to acquire after triggering sample.
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0x03: thresh_value (RW)
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Minimum peak to peak value considered triggered
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0x04: thresh_time (RW)
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Number of consecutive samples above threshold required to consider triggered
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0x05: decay_value (RW)
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Decay value to subtract from peak values to prevent false triggers
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0x06: decay_period (RW)
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Number of samples between each application of decay
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0x1xx: BUFFER_LEN_X (RO)
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Lenght of data in buffer, up to the number of samplers provided.
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"""
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def __init__(self, samplers: List[Sampler], buffer_len):
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self.samplers = samplers
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num_channels = len(samplers)
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# Enables reading in samples
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sample_enable = Signal()
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# Pull in only one CDC sync signal
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sample_ready = self.samplers[0].valid
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# Generate buffers for each sampler
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self.buffers = [CircularBuffer(9, buffer_len) for _ in range(num_channels)]
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# Connect each buffer to each sampler
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for buffer, sampler in zip(self.buffers, self.samplers):
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self.submodules += buffer
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self.submodules += sampler
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self.comb += [
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# Connect only top 9 bits to memory
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buffer.wr_data.eq(sampler.data[1:]),
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# Writes enter FIFO only when enabled and every clock cycle
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buffer.wr_valid.eq(sample_enable & sample_ready),
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]
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# Each sampler gets some chunk of memory at least large enough to fit
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# all of it's data, so use that as a consistent offset. Use a minimum
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# address of 0x800 to avoid conflicts with control registers
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sample_mem_addr_width = max(ceil(log2(buffer_len)), ceil(log2(0x800)))
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# 1 control block + number of channels used = control bits
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control_block_addr_width = ceil(log2(num_channels + 1))
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# Bus address width
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addr_width = control_block_addr_width + sample_mem_addr_width
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# "Master" bus
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self.bus = Interface(data_width=32, addr_width=addr_width)
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# Wishbone bus used for mapping control registers
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self.control_regs_bus = Interface(data_width=32, addr_width=sample_mem_addr_width)
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slaves = []
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slaves.append((lambda adr: adr[sample_mem_addr_width:] == 0, self.control_regs_bus))
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for i, buffer in enumerate(self.buffers):
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# Connect subordinate buses of buffers to decoder
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slaves.append((lambda adr: adr[sample_mem_addr_width:] == i + 1, buffer.bus))
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adr = (i + 1) << sample_mem_addr_width
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print(f"Sampler {i} available at 0x{adr:08x}")
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self.submodules.decoder = Decoder(self.bus, slaves)
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self.submodules.peak_detector = PeakDetector(10)
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self.comb += [
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# Simply enable whenever we start capturing
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self.peak_detector.enable.eq(sample_enable),
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# Connect to the first ADC
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self.peak_detector.data.eq(self.samplers[0].data),
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# Use the same criteria as the fifo buffer
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self.peak_detector.data_valid.eq(sample_enable & sample_ready),
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]
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#### Control register logic
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# Storage
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control_register = Signal(32)
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status_register = Signal(32)
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trigger_run_len = Signal(32)
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def rw_register(storage: Signal, *, read: bool = True, write: bool = True):
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if read:
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read = self.control_regs_bus.dat_r.eq(storage)
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else:
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read = self.control_regs_bus.ack.eq(0)
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if write:
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write = storage.eq(self.control_regs_bus.dat_w)
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else:
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write = self.control_regs_bus.ack.eq(0)
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return If(self.control_regs_bus.we, write).Else(read)
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# Handle explicit config registers
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cases = {
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0: rw_register(control_register),
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1: rw_register(status_register, write=False),
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2: rw_register(trigger_run_len),
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3: rw_register(self.peak_detector.thresh_value),
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4: rw_register(self.peak_detector.thresh_time),
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5: rw_register(self.peak_detector.decay_value),
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6: rw_register(self.peak_detector.decay_period),
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"default": rw_register(None, read=False, write=False)
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}
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# Handle length values for each sample buffer
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for i, buffer in enumerate(self.buffers):
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cases.update({0x100 + i: rw_register(buffer.len, write=False)})
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# Connect up control registers bus
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self.sync += [
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self.control_regs_bus.ack.eq(0),
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If(self.control_regs_bus.cyc & self.control_regs_bus.stb,
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self.control_regs_bus.ack.eq(1),
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Case(self.control_regs_bus.adr, cases)),
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]
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# Handle the control logic
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post_trigger_count = Signal(32)
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self.sync += [
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# Reset state whenever sampling is disabled
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If(~sample_enable, post_trigger_count.eq(0)),
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# Reset triggering status if we have started sampling
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# (peak_detector.triggered resets if sample_enable is de-asserted, so
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# this is a reliable reset mechanism)
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If(sample_enable & ~self.peak_detector.triggered,
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status_register[0].eq(0)),
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# Keep sampling past the trigger for the configured number of samples
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If(self.peak_detector.triggered & sample_enable & sample_ready,
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post_trigger_count.eq(post_trigger_count + 1),
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# We have sampled enough, update status and stop sampling
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If(post_trigger_count + 1 >= trigger_run_len,
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status_register[0].eq(1),
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control_register[0].eq(0))),
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]
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# Update register storage
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self.comb += [
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sample_enable.eq(control_register[0]),
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]
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def write_wishbone(bus, address, value):
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# Set up bus
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(yield bus.adr.eq(address))
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(yield bus.dat_w.eq(value))
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(yield bus.stb.eq(1))
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(yield bus.cyc.eq(1))
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(yield bus.we.eq(1))
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yield
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cycles = 0
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while True:
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cycles += 1
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assert cycles < 5, "Write fail"
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if (yield bus.ack) == 1:
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# We received a response, clear out bus status and exit
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(yield bus.stb.eq(0))
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(yield bus.cyc.eq(0))
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yield
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break
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else:
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# Tick until we receive an ACK
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yield
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def read_wishbone(bus, address,):
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"""Sets up a read transaction. Due to limitations of the simulation method, you have to read
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from dat_r, and also tick immediately after calling"""
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# Set up bus
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(yield bus.adr.eq(address))
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(yield bus.stb.eq(1))
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(yield bus.cyc.eq(1))
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(yield bus.we.eq(0))
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yield
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cycles = 0
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while True:
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cycles += 1
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assert cycles < 5, "Write fail"
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if (yield bus.ack) == 1:
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# We received a response, clear out bus status and exit
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(yield bus.stb.eq(0))
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(yield bus.cyc.eq(0))
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yield # Tick
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break
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else:
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# Tick until we receive an ACK
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yield
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class MockSampler(Module):
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"""
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Attributes
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----------
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All Sampler attributes by default, plus the following:
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index:
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Index of data to use from provided data
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"""
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def __init__(self, data: List[int]):
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self.specials.memory = Memory(width=10, depth=len(data), init=data)
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self.index = Signal(ceil(log2(len(data))))
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self.data = Signal(10)
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self.valid = Signal()
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read_port = self.memory.get_port(async_read=True)
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self.comb += [
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read_port.adr.eq(self.index),
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self.data.eq(read_port.dat_r),
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]
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class TestSoC(Module):
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def __init__(self, data: List[int], *, buffer_len: int = 1024, num_samplers: int = 1):
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# TODO multiple mock samplers to test that functionality
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self.samplers = [MockSampler(data) for _ in range(num_samplers)]
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self.controller = SamplerController(self.samplers, buffer_len)
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self.submodules.controller = self.controller
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self.bus = self.controller.bus
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def test_bus_access():
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dut = TestSoC([2, 3, 4, 5])
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def test_fn():
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yield from write_wishbone(dut.bus, 2, 0xDEADBEEF)
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yield from read_wishbone(dut.bus, 2)
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assert (yield dut.bus.dat_r) == 0xDEADBEEF, "Read failed!"
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# TODO test writing to RO register fails
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run_simulation(dut, test_fn(), vcd_name="test_bus_access.vcd")
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def test_simple_waveform():
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"""End-to-end test of a simple waveform"""
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from .peak_detector import create_waveform
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_, data = create_waveform()
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data = [int(d) for d in data]
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dut = TestSoC(data, buffer_len=32)
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def test_fn():
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# Set settings
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yield from write_wishbone(dut.bus, 2, 0) # trigger_run_len = 0
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yield from write_wishbone(dut.bus, 3, 800) # thresh_value = 800
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yield from write_wishbone(dut.bus, 4, 10) # thresh_time = 10
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yield from write_wishbone(dut.bus, 5, 1) # decay_value = 1
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yield from write_wishbone(dut.bus, 5, 0) # decay_period = 0
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# Start controller
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yield from write_wishbone(dut.bus, 0, 1)
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triggered_yet = False
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triggered_num = 0
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for i in range(1000):
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(yield dut.samplers[0].index.eq(i))
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(yield dut.samplers[0].valid.eq(1))
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yield
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(yield dut.samplers[0].valid.eq(0))
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yield
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# Total of 6 clocks per sample clock
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yield
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yield
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yield
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yield
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if not triggered_yet and (yield dut.controller.peak_detector.triggered) == 1:
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# Triggered, now we need to run some number of cycles
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triggered_yet = True
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if triggered_yet:
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triggered_num += 1
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if triggered_num > 32:
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# We should now have collected all our samples
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yield from read_wishbone(dut.bus, 1)
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assert (yield dut.bus.dat_r) == 1, "Trigger did not propogate to WB!"
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# Check that length is correct
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yield from read_wishbone(dut.bus, 0x100)
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len = (yield dut.bus.dat_r)
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assert len == 32, f"Len ({len}) not correct!"
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# Read data in
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data = []
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for i in range(32):
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yield from read_wishbone(dut.bus, 0x800 + i)
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sample = (yield dut.bus.dat_r)
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data.append(sample)
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# Test pass
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return
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assert False, "We should have triggered"
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run_simulation(dut, test_fn())
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def test_simple_waveform_capture_offset():
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"""Test a simple waveform captured at an offset"""
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from .peak_detector import create_waveform
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_, data = create_waveform()
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data = [int(d) for d in data]
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dut = TestSoC(data, buffer_len=32)
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def test_fn():
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# Set settings
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yield from write_wishbone(dut.bus, 2, 16) # trigger_run_len = 16
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yield from write_wishbone(dut.bus, 3, 800) # thresh_value = 800
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yield from write_wishbone(dut.bus, 4, 10) # thresh_time = 10
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yield from write_wishbone(dut.bus, 5, 1) # decay_value = 1
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yield from write_wishbone(dut.bus, 5, 0) # decay_period = 0
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# Start controller
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yield from write_wishbone(dut.bus, 0, 1)
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triggered_yet = False
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triggered_num = 0
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for i in range(1000):
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(yield dut.samplers[0].index.eq(i))
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(yield dut.samplers[0].valid.eq(1))
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yield
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(yield dut.samplers[0].valid.eq(0))
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yield
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# Total of 6 clocks per sample clock
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yield
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yield
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yield
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yield
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if not triggered_yet and (yield dut.controller.peak_detector.triggered) == 1:
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# Triggered, now we need to run some number of cycles
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triggered_yet = True
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if triggered_yet:
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triggered_num += 1
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if triggered_num > 16:
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# We should now have collected all our samples
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yield from read_wishbone(dut.bus, 1)
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assert (yield dut.bus.dat_r) == 1, "Trigger did not propogate to WB!"
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# Check that length is correct
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yield from read_wishbone(dut.bus, 0x100)
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len = (yield dut.bus.dat_r)
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assert len == 32, f"Len ({len}) not correct!"
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# Read data in
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data = []
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for i in range(32):
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yield from read_wishbone(dut.bus, 0x800 + i)
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sample = (yield dut.bus.dat_r)
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data.append(sample)
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# Manually validated from test above to be offset into the
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# data
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assert data[0] == 138
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assert data[1] == 132
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# Test pass
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return
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assert False, "We should have triggered"
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run_simulation(dut, test_fn())
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